gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef IOTE_RZA2M
   16: 
   17: /*
   18:  *      hw_setting.c (RZ/A2M IoT-Engine)
   19:  *              hardware settings
   20:  */
   21: 
   22: #include "kernel.h"
   23: #include <tm/tmonitor.h>
   24: 
   25: #include "sysdepend.h"
   26: 
   27: /* 
   28:  * Setup register data 
   29:  */
   30: typedef struct {
   31:         UW     addr;
   32:         UB     data;
   33: } T_SETUP_REG;
   34: 
   35: /* Setting the clock supply to each module */
   36: LOCAL const T_SETUP_REG stbcr_tbl[] = {
   37:         {CPG_STBCR3 , 0b10001101},     /* [1], OSTM0, OSTM1, OSTM2, MTU3, CAN-FD, [0], GPT */
   38:         {CPG_STBCR4 , 0b11110111},     /* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCI0, SCI1,IrDA */
   39: /* When all devices are enabled */
   40: //      {CPG_STBCR2 , 0x6A}, /* Port level is keep in standby mode, [1], [1], [0], [1], [0], [1], CoreSight */
   41: //      {CPG_STBCR3 , 0x80}, /* [1], OSTM0, OSTM1, OSTM3, MTU3, CAN-FD, [0], GPT */
   42: //      {CPG_STBCR4 , 0x00}, /* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCI0, SCI1,IrDA */
   43: //      {CPG_STBCR5 , 0x31}, /* A/D, CEU, [1], [1], RTC0, RTC1, JCU, [1] */
   44: //      {CPG_STBCR6 , 0x80}, /* [1], VIN, ETHER0, ETHER1, EtherPTR, EtherM, USB0, USB1 */
   45: //      {CPG_STBCR7 , 0x10}, /* IMR-LS2, DAVE-2D, MIPI, [1], SSIF0, SSIF1, SSIF2, SSIF3 */
   46: //      {CPG_STBCR8 , 0x05}, /* IIC0, IIC1, IIC2, IIC3, SPIBSC, [1], VDC6, [1] */
   47: //      {CPG_STBCR9 , 0x11}, /* RSPI0, RSPI1, RSPI2, [1], HYPER, OCTA, SPDIF, DRP */
   48: //      {CPG_STBCR10, 0x00}, /* TSIP, [0], [0], NAND, SDHI00, SDHI01, SDHI10, SDHI11 */
   49: //      {CPG_STBCR11, 0x3F}, /* POE3, POEG, [1], [1], [1], [1], [1] , [1] */
   50: 
   51:         {0, 0}
   52: };
   53: 
   54: /* Pin mode Tadle */
   55: LOCAL const T_SETUP_REG pmode_tbl[] = {
   56:         // Serial debug I/F : P90 -> TxD4, P91 -> RxD4
   57:         {PORT9_PMR, 0b00000011},
   58: 
   59:         {0, 0}
   60: };
   61: 
   62: /* Pin function Tadle */
   63: LOCAL const T_SETUP_REG pfunc_tbl[] = {
   64:         // Serial debug I/F : P90 -> TxD4, P91 -> RxD4
   65:         {PORT9n_PFS(0), 0x04},
   66:         {PORT9n_PFS(1), 0x04},
   67: 
   68:         {0, 0}
   69: };
   70: 
   71: /*
   72:  * Startup hardware
   73:  */
   74: EXPORT void knl_startup_hw(void)
   75: {
   76:         const T_SETUP_REG      *p;
   77:         _UB                    dummy_b;
   78: 
   79:         /* Startup System Clock (CPG settings) */
   80:         startup_clock();
   81: 
   82:         /* Setting the clock supply to each module */
   83:         for(p = stbcr_tbl; p->addr != 0; p++) {
   84:                 out_b(p->addr, p->data);
   85:                 dummy_b = in_b(p->addr);
   86:         }
   87:         dummy_b;
   88: 
   89:         /* Pin mode selection */
   90:         for(p = pmode_tbl; p->addr != 0; p++) {
   91:                 or_b(p->addr, p->data);
   92:         }
   93: 
   94:         /* Pin function selection */
   95:         out_b(PORT_PWPR, 0);
   96:         out_b(PORT_PWPR, PORT_PWPR_PFSWE);             /* Allow writing to PFS */
   97:         for(p = pfunc_tbl; p->addr != 0; p++) {
   98:                 out_b(p->addr, p->data);
   99:         }
  100:         out_b(PORT_PWPR, PORT_PWPR_B0WI);              /* Prohibit writing to PFS */
  101: }
  102: 
  103: #if USE_SHUTDOWN
  104: /*
  105:  * Shutdown hardware
  106:  */
  107: EXPORT void knl_shutdown_hw( void )
  108: {
  109:         disint();
  110:         shutdown_clock();
  111: 
  112:         while(1);
  113: }
  114: #endif /* USE_SHUTDOWN */
  115: 
  116: /*
  117:  * Re-start hardware
  118:  *      mode = -1            reset and re-start        (Reset -> Boot -> Start)
  119:  *      mode = -2            fast re-start             (Start)
  120:  *      mode = -3            Normal re-start           (Boot -> Start)
  121:  */
  122: EXPORT ER knl_restart_hw( W mode )
  123: {
  124:         switch(mode) {
  125:         case -1: /* Reset and re-start */
  126:                 SYSTEM_MESSAGE("\n<< SYSTEM RESET & RESTART >>\n");
  127:                 return E_NOSPT;
  128:         case -2: /* fast re-start */
  129:                 SYSTEM_MESSAGE("\n<< SYSTEM FAST RESTART >>\n");
  130:                 return E_NOSPT;
  131:         case -3: /* Normal re-start */
  132:                 SYSTEM_MESSAGE("\n<< SYSTEM RESTART >>\n");
  133:                 return E_NOSPT;
  134:         default:
  135:                 return E_PAR;
  136:         }
  137: }
  138: 
  139: #endif  /* IOTE_RZA2M */