gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.03
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/03/31.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_CORE_ARMV7M
   16: 
   17: /*
   18:  *      int_armv7m.c
   19:  *
   20:  *      Interrupt controller (ARMv7-M)
   21:  */
   22: 
   23: #include <tk/tkernel.h>
   24: 
   25: #include "int_armv7m.h"
   26: 
   27: /*----------------------------------------------------------------------*/
   28: /*
   29:  * CPU Interrupt Control for ARM Cortex-M4.
   30:  *
   31:  */
   32: 
   33: /*
   34:  * Set Base Priority register
   35:  */
   36: EXPORT void set_basepri(UW intsts)
   37: {       
   38:         Asm("msr basepri, %0":: "r"(intsts));
   39: }
   40: 
   41: /*
   42:  * Get Base Priority register
   43:  */
   44: EXPORT UW get_basepri(void)
   45: {
   46:         UW     basepri;
   47: 
   48:         Asm("mrs %0, basepri": "=r"(basepri));
   49:         return basepri;
   50: }
   51: 
   52: /* 
   53:  * Disable interrupt 
   54:  */
   55: EXPORT UW disint(void)
   56: {
   57:         UW     intsts, maxint;
   58: 
   59:         maxint = INTPRI_VAL(INTPRI_MAX_EXTINT_PRI);
   60:         Asm("mrs %0, basepri": "=r"(intsts));
   61:         Asm("msr basepri, %0":: "r"(maxint));
   62: 
   63:         return intsts;
   64: }
   65: 
   66: /*
   67:  * Set Interrupt Mask Level in CPU
   68:  */
   69: EXPORT void SetCpuIntLevel( INT level )
   70: {
   71:         set_basepri((level+1) << (8-INTPRI_BITWIDTH));
   72: }
   73: 
   74: /*
   75:  * Get Interrupt Mask Level in CPU
   76:  */
   77: EXPORT INT GetCpuIntLevel( void )
   78: {
   79:         INT    lv;
   80: 
   81:         lv = (INT)(get_basepri() >>(8-INTPRI_BITWIDTH)) -1;
   82:         return lv<0?INTLEVEL_EI:lv;
   83: }
   84: 
   85: 
   86: /*----------------------------------------------------------------------*/
   87: /*
   88:  * Interrupt controller (NVIC) Control
   89:  *
   90:  */
   91: 
   92: /*
   93:  * Enable interrupt for NVIC
   94:  */
   95: EXPORT void EnableInt_nvic( UINT intno, INT level )
   96: {
   97:         UINT   imask;
   98:         
   99:         DI(imask);
  100:         /* Set interrupt priority level. */
  101:         *(_UB*)(NVIC_IPR(intno)) = (UB)INTPRI_GROUP(level, 0);
  102: 
  103:         /* Enables the specified interrupt. */
  104:         *(_UW*)(NVIC_ISER(intno)) = (0x01U << (intno % 32));
  105: 
  106:         EI(imask);
  107: }
  108: 
  109: 
  110: 
  111: #endif /* CPU_CORE_ARMV7M */