gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.01
    4:  *
    5:  *    Copyright (C) 2006-2020 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2020/05/29.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_CORE_RXV2
   16: 
   17: /*
   18:  *      int_rxv2.c
   19:  *
   20:  *      Interrupt control (RXv2 Core)
   21:  */
   22: 
   23: #include <tk/tkernel.h>
   24: 
   25: /*----------------------------------------------------------------------*/
   26: /*
   27:  * CPU Interrupt Control for RXv2 core.
   28:  *
   29:  */
   30: #define PSW_IPL_MASK            0x0F000000
   31: 
   32: /* 
   33:  * Disable interrupt (Set PSW.IPL value to 15. And return the original PSW.IPL value.)
   34:  */
   35: EXPORT UW disint(void)
   36: {
   37:         UW     psw, ans;
   38: 
   39:         Asm("mvfc psw, %0": "=r"(psw));
   40: 
   41:         ans = (psw & PSW_IPL_MASK) >> 24;
   42:         psw = (psw & ~PSW_IPL_MASK) |(INTPRI_MAX_INT_PRI << 24);
   43: 
   44:         Asm("mvtc %0, psw":: "r"(psw));
   45: 
   46:         return ans;
   47: }
   48: 
   49: /* 
   50:  * Set interrupt level (Set PSW.IPL value to ipl.)
   51:  */
   52: EXPORT void setint(UW ipl)
   53: {
   54:         UW     psw;
   55: 
   56:         Asm("mvfc psw, %0": "=r"(psw));
   57: 
   58:         psw = (psw & ~PSW_IPL_MASK) |(ipl << 24);
   59: 
   60:         Asm("mvtc %0, psw":: "r"(psw));
   61: }
   62: 
   63: /*
   64:  * Set Interrupt Mask Level in CPU
   65:  */
   66: EXPORT void SetCpuIntLevel( INT level )
   67: {
   68:         level--;
   69:         if(level >= INTLEVEL_EI && level <= INTLEVEL_DI) {
   70:                 setint(level);
   71:         }
   72: }
   73: 
   74: /*
   75:  * Get Interrupt Mask Level in CPU
   76:  */
   77: EXPORT INT GetCpuIntLevel( void )
   78: {
   79:         UW     psw;
   80: 
   81:         Asm("mvfc psw, %0": "=r"(psw));
   82: 
   83:         return ((psw & PSW_IPL_MASK) >> 24) + 1;
   84: }
   85: 
   86: 
   87: /*----------------------------------------------------------------------*/
   88: /*
   89:  * Interrupt controller (ICUb) Control
   90:  *
   91:  */
   92: 
   93: IMPORT const H  IPR_index[];
   94: 
   95: /*
   96:  * Enable interrupt 
   97:  *      Enables the interrupt specified in intno.
   98:  *      External Interrupt can be specified. 
   99:  */
  100: EXPORT void EnableInt( UINT intno, INT level )
  101: {
  102:         UINT   imask;
  103: 
  104:         if((intno < 16) && (intno > 255)) {
  105:                 return;
  106:         }
  107: 
  108:         DI(imask);
  109: 
  110:         if( IPR_index[intno-16] >= 0 ){
  111:         /* Disable the interrupt before set priority level. */
  112:                 *(_UB*)(ICU_IER(intno)) &= ~ICU_IER_IEN(intno);
  113:         /* Set interrupt priority level. */
  114:                 *(_UB*)(ICU_IPR(IPR_index[intno-16])) = (UB)level;
  115:         /* Enables the specified interrupt. */
  116:                 *(_UB*)(ICU_IER(intno)) |= ICU_IER_IEN(intno);
  117:         }
  118: 
  119:         EI(imask);
  120: }
  121: 
  122: /*
  123:  * Disable interrupt 
  124:  *      Disables the interrupt specified in intno.
  125:  *      External Interrupt can be specified. 
  126:  */
  127: EXPORT void DisableInt( UINT intno )
  128: {
  129:         if((intno < 16) && (intno > 255)) {
  130:                 return;
  131:         }
  132: 
  133:         if( IPR_index[intno-16] >= 0){
  134:         /* Disable the interrupt before set priority level. */
  135:                 *(_UB*)(ICU_IER(intno)) &= ~ICU_IER_IEN(intno);
  136:         }
  137: }
  138: 
  139: /*
  140:  * Clear interrupt
  141:  *      Clear the interrupt specified in intno.
  142:  *      External Interrupt can be specified. 
  143:  */
  144: EXPORT void ClearInt( UINT intno )
  145: {
  146:         *(_UB*)(ICU_IR(intno)) = 0;
  147: }
  148: 
  149: /*
  150:  * Issue EOI to interrupt controller
  151:  */
  152: EXPORT void EndOfInt(UINT intno)
  153: {
  154:         /* No opetarion. */
  155: }
  156: 
  157: /*
  158:  * Check active state
  159:  *      Current active state for the associated interrupt
  160:  *      External Interrupt can be specified. 
  161:  */
  162: EXPORT BOOL CheckInt( UINT intno )
  163: {
  164:         return (*(_UB*)(ICU_IR(intno)));
  165: }
  166: 
  167: /*
  168:  * Set interrupt mode
  169:  */
  170: EXPORT void SetIntMode(UINT intno, UINT mode)
  171: {
  172:         UINT   imask;
  173:         UB     irqmd;
  174: 
  175:         switch (mode) {
  176:         case (IM_LEVEL | IM_LOW):
  177:                 irqmd = 0x00;
  178:                 break;
  179:         case (IM_EDGE | IM_LOW):
  180:                 irqmd = 0x04;
  181:                 break;
  182:         case (IM_EDGE | IM_HI):
  183:                 irqmd = 0x80;
  184:                 break;
  185:         case (IM_EDGE | IM_BOTH):
  186:                 irqmd = 0xC0;
  187:                 break;
  188:         default:
  189:                 return;
  190:         }
  191: 
  192:         DI(imask);
  193: 
  194:         if(IPR_index[intno] >= 0){
  195:         /* Disable the interrupt before set priority level. */
  196:                 *(_UB*)(ICU_IER(intno)) &= ~ICU_IER_IEN(intno);
  197:         /* Set interrupt priority level. */
  198:                 *(_UB*)(ICU_IRQCR(intno)) = irqmd;
  199:         /* Enables the specified interrupt. */
  200:                 *(_UB*)(ICU_IER(intno)) |= ICU_IER_IEN(intno);
  201:         }
  202: 
  203:         EI(imask);
  204: }
  205: 
  206: 
  207: #endif /* CPU_CORE_RXV2 */