gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.04
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/05/17.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: #include <sys/machine.h>
   15: #ifdef CPU_TMPM367FDFG
   16: /*
   17:  *      ptimer_m367.c
   18:  *
   19:  *      Physical timer (for TX03M67 TMRB)
   20:  */
   21: #include <tk/tkernel.h>
   22: #include <tk/syslib.h>
   23: 
   24: #if USE_PTMR
   25: 
   26: typedef struct {
   27:         UW     baddr;              // Register Base Address
   28:         UINT   mode;             // Timer mode
   29:         UW     limit;              // Counter Limit
   30:         FP     ptmrhdr;    // Timer Hnadler
   31:         PRI    intptr;            // Interrupt priority
   32:         UW     clock;              // Source clock
   33:         void   *exinf;           // Extended information
   34: } T_PTMRCB;
   35: 
   36: T_PTMRCB ptmrcb[TK_MAX_PTIMER] = {
   37:         { TMRB0_BASE, -1, 0, (FP)NULL, INTPRI_TMRB0, TB0MOD_TBCLK, 0 },
   38:         { TMRB1_BASE, -1, 0, (FP)NULL, INTPRI_TMRB1, TB1MOD_TBCLK, 0 },
   39:         { TMRB2_BASE, -1, 0, (FP)NULL, INTPRI_TMRB2, TB2MOD_TBCLK, 0 },
   40:         { TMRB3_BASE, -1, 0, (FP)NULL, INTPRI_TMRB3, TB3MOD_TBCLK, 0 },
   41:         { TMRB4_BASE, -1, 0, (FP)NULL, INTPRI_TMRB4, TB4MOD_TBCLK, 0 },
   42:         { TMRB5_BASE, -1, 0, (FP)NULL, INTPRI_TMRB5, TB5MOD_TBCLK, 0 },
   43:         { TMRB6_BASE, -1, 0, (FP)NULL, INTPRI_TMRB6, TB6MOD_TBCLK, 0 },
   44:         { TMRB7_BASE, -1, 0, (FP)NULL, INTPRI_TMRB7, TB7MOD_TBCLK, 0 }
   45: };
   46: 
   47: #define TMRB_TBxEN      (p_cb->baddr + TBxEN)
   48: #define TMRB_TBxRUN     (p_cb->baddr + TBxRUN)
   49: #define TMRB_TBxFFCR    (p_cb->baddr + TBxFFCR)
   50: #define TMRB_TBxMOD     (p_cb->baddr + TBxMOD)
   51: #define TMRB_TBxRG1     (p_cb->baddr + TBxRG1)
   52: #define TMRB_TBxIM      (p_cb->baddr + TBxIM)
   53: #define TMRB_TBxUC      (p_cb->baddr + TBxUC)
   54: 
   55: /*
   56:  * Physical timer interrupt handler
   57:  */
   58: LOCAL void ptmr_int_main( UINT intno, T_PTMRCB *p_cb)
   59: {
   60:         ClearInt( intno);
   61:         if( p_cb->ptmrhdr != NULL) {
   62:                 (*p_cb->ptmrhdr)( p_cb->exinf);               // Execute user handler.
   63:         }
   64: 
   65:         if( p_cb->mode == TA_ALM_PTMR)  {
   66:                 /* Stop Pysical timer */
   67:                 DisableInt( intno);
   68:                 out_w( TMRB_TBxEN, TBxEN_TBEN );      // Timer module disabled.
   69:         }
   70: }
   71: 
   72: LOCAL void ptmr1_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[0]); }
   73: LOCAL void ptmr2_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[1]); }
   74: LOCAL void ptmr3_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[2]); }
   75: LOCAL void ptmr4_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[3]); }
   76: LOCAL void ptmr5_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[4]); }
   77: LOCAL void ptmr6_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[5]); }
   78: LOCAL void ptmr7_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[6]); }
   79: LOCAL void ptmr8_inthdr( UINT intno ) { ptmr_int_main( intno, &ptmrcb[7]); }
   80: 
   81: LOCAL void (* const inthdr_tbl[])() = {
   82:         ptmr1_inthdr, ptmr2_inthdr, ptmr3_inthdr, ptmr4_inthdr, ptmr5_inthdr,
   83:         ptmr6_inthdr, ptmr7_inthdr, ptmr8_inthdr
   84: };
   85: 
   86: LOCAL const UINT intno_tbl[] = {
   87:         INTNO_TMRB0, INTNO_TMRB1, INTNO_TMRB2, INTNO_TMRB3, INTNO_TMRB4,
   88:         INTNO_TMRB5, INTNO_TMRB6, INTNO_TMRB7
   89: };
   90: 
   91: /*
   92:  * Start of physical timer operation
   93:  */
   94: EXPORT ER StartPhysicalTimer( UINT ptmrno, UW limit, UINT mode)
   95: {
   96:         T_DINT         dint;
   97:         T_PTMRCB       *p_cb;
   98:         UINT           intno;
   99:         ER             err;
  100: 
  101:         /* parameter check */
  102:         if(( ptmrno == 0 || ptmrno > TK_MAX_PTIMER ) || ( limit == 0 || limit > PTMR_MAX_CNT )
  103:                 || ( mode > TA_CYC_PTMR ))    return E_PAR;
  104: 
  105:         p_cb = &ptmrcb[ptmrno - 1];
  106:         p_cb->limit    = limit;
  107:         p_cb->mode     = mode;
  108: 
  109:         /* Timer initialization */
  110:         out_w( TMRB_TBxEN, TBxEN_TBEN );       // Timer module enabled.
  111:         out_w( TMRB_TBxRUN , 0);               // Stop Timer & Counter clear.
  112:         out_w( TMRB_TBxFFCR, TBxFFCR_TDE);     // Trigger disable
  113: 
  114:         if( limit != PTMR_MAX_CNT ) {
  115:                 out_w( TMRB_TBxMOD , TBxMOD_TBCLE | p_cb->clock);     // Set Clock & Up-Counter control.
  116:                 out_w( TMRB_TBxRG1 ,  limit + 1);                     // Set limit time.
  117:                 out_w( TMRB_TBxIM, TBxIM_TBIMOF | TBxIM_TBIM0 );      // Set interrupt mask.
  118:         } else {
  119:                 out_w( TMRB_TBxMOD , p_cb->clock);                    // Set Clock.
  120:                 out_w( TMRB_TBxIM, TBxIM_TBIM1 | TBxIM_TBIM0 );               // Set interrupt mask
  121:         }
  122: 
  123:         /* Register interrupt handler */
  124:         intno          = intno_tbl[ptmrno - 1];
  125:         dint.intatr    = TA_HLNG;
  126:         dint.inthdr    = inthdr_tbl[ptmrno - 1];
  127:         err = tk_def_int( intno, &dint);
  128:         if(err != E_OK) {
  129:                 return err;
  130:         }
  131:         EnableInt( intno, p_cb->intptr);
  132: 
  133:         /* Start Physical Timer */
  134:         out_w( TMRB_TBxRUN , TBxRUN_TBRUN | TBxRUN_TBPRUN );   // Start Timer.
  135: 
  136:         return E_OK;
  137: }
  138: 
  139: EXPORT ER StopPhysicalTimer( UINT ptmrno )
  140: {
  141:         T_PTMRCB       *p_cb;
  142: 
  143:         /* parameter check */
  144:         if( ptmrno == 0 || ptmrno > TK_MAX_PTIMER ) return E_PAR;
  145: 
  146:         p_cb = &ptmrcb[ptmrno - 1];
  147: 
  148:         /* Stop Physical Timer */
  149:         DisableInt( intno_tbl[ptmrno - 1]);
  150:         out_w( TMRB_TBxEN, TBxEN_TBEN );       // Timer module disabled.
  151: 
  152:         return E_OK;
  153: }
  154: 
  155: 
  156: IMPORT ER GetPhysicalTimerCount( UINT ptmrno, UW *p_count )
  157: {
  158:         T_PTMRCB       *p_cb;
  159: 
  160:         /* parameter check */
  161:         if( ptmrno == 0 || ptmrno > TK_MAX_PTIMER ) return E_PAR;
  162: 
  163:         p_cb = &ptmrcb[ptmrno - 1];
  164: 
  165:         /* Get Physical timer counter */
  166:         *p_count = in_w( TMRB_TBxUC ); // Read counter.
  167: 
  168:         return E_OK;
  169: }
  170: 
  171: 
  172: EXPORT ER DefinePhysicalTimerHandler( UINT ptmrno, CONST T_DPTMR *pk_dptmr )
  173: {
  174:         T_PTMRCB       *p_cb;
  175: 
  176:         /* parameter check */
  177:         if( ptmrno == 0 || ptmrno > TK_MAX_PTIMER ) return E_PAR;
  178: 
  179:         p_cb = &ptmrcb[ptmrno - 1];
  180: 
  181:         /* Set user Handler */
  182:         if(pk_dptmr != NULL) {
  183:                 p_cb->ptmrhdr = pk_dptmr->ptmrhdr;
  184:                 p_cb->exinf   = pk_dptmr->exinf;
  185:         } else {
  186:                 p_cb->ptmrhdr = NULL;
  187:         }
  188: 
  189:         return E_OK;
  190: }
  191: 
  192: 
  193: EXPORT ER GetPhysicalTimerConfig(UINT ptmrno, T_RPTMR *pk_rptmr)
  194: {
  195:         T_PTMRCB       *p_cb;
  196:         UW             ptmrclk;
  197: 
  198:         /* parameter check */
  199:         if( ptmrno == 0 || ptmrno > TK_MAX_PTIMER ) return E_PAR;
  200: 
  201:         p_cb = &ptmrcb[ptmrno - 1];
  202: 
  203:         switch(p_cb->clock) {
  204:         case 0x00000001:
  205:                 ptmrclk = (CLOCK_fc / 4);     // fc/2^2
  206:                 break;
  207:         case 0x00000010:
  208:                 ptmrclk = (CLOCK_fc / 16);    // fc/2^4
  209:                 break;
  210:         case 0x00000011:
  211:                 ptmrclk = (CLOCK_fc / 64);    // fc/2^6
  212:                 break;
  213:         case 0x00000100:
  214:                 ptmrclk = (CLOCK_fc / 128);   // fc/2^7
  215:                 break;
  216:         case 0x00000101:
  217:                 ptmrclk = (CLOCK_fc / 256);   // fc/2^8
  218:                 break;
  219:         case 0x00000110:
  220:                 ptmrclk = (CLOCK_fc / 512);   // fc/2^9
  221:                 break;
  222:         case 0x00000111:
  223:                 ptmrclk = (CLOCK_fc / 1024);  // fc/2^10
  224:                 break;
  225:         default:
  226:                 ptmrclk = 0;                  // Unknown
  227:         }
  228:         pk_rptmr->ptmrclk      = ptmrclk;
  229:         pk_rptmr->maxcount     = PTMR_MAX_CNT;
  230:         pk_rptmr->defhdr       = TRUE;
  231: 
  232:         return E_OK;
  233: }
  234: 
  235: #endif  /* USE_PTMR */
  236: #endif  /* CPU_TMPM367FDFG */