gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    micro T-Kernel 3.00.05
    4:  *
    5:  *    Copyright (C) 2006-2021 by Ken Sakamura.
    6:  *    This software is distributed under the T-License 2.2.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by TRON Forum(http://www.tron.org) at 2021/11.
   10:  *
   11:  *----------------------------------------------------------------------
   12:  */
   13: 
   14: /*
   15:  *    tm_com.c
   16:  *    T-Monitor Communication low-level device driver (RZ/A2M IoT-Engine)
   17:  */
   18: 
   19: #include <tk/tkernel.h>
   20: 
   21: #if USE_TMONITOR
   22: #include "../../libtm.h"
   23: 
   24: #ifdef IOTE_RZA2M
   25: #if TM_COM_SERIAL_DEV
   26: 
   27: /* SCIFA register definition (Use SCIFA4) */
   28: #define SCIFA_BASE      0xE8009000   /* SCIFA4 register base address */
   29: #define SCIFA_SMR       (SCIFA_BASE + 0x0000)
   30: #define SCIFA_BRR       (SCIFA_BASE + 0x0002)
   31: #define SCIFA_SCR       (SCIFA_BASE + 0x0004)
   32: #define SCIFA_FTDR      (SCIFA_BASE + 0x0006)
   33: #define SCIFA_FSR       (SCIFA_BASE + 0x0008)
   34: #define SCIFA_FRDR      (SCIFA_BASE + 0x000A)
   35: #define SCIFA_FCR       (SCIFA_BASE + 0x000C)
   36: #define SCIFA_FDR       (SCIFA_BASE + 0x000E)
   37: #define SCIFA_SPTR      (SCIFA_BASE + 0x0010)
   38: #define SCIFA_LSR       (SCIFA_BASE + 0x0012)
   39: #define SCIFA_SEMR      (SCIFA_BASE + 0x0014)
   40: #define SCIFA_FTCR      (SCIFA_BASE + 0x0016)
   41: 
   42: #define SCR_TE          0x0020
   43: #define SCR_RE          0x0010
   44: 
   45: #define FSR_ER          0x0080
   46: #define FSR_TEND        0x0040
   47: #define FSR_TDFE        0x0020
   48: #define FSR_BRK         0x0010
   49: #define FSR_FER         0x0008
   50: #define FSR_PER         0x0004
   51: #define FSR_RDF         0x0002
   52: #define FSR_DR          0x0001
   53: #define FSR_ERROR       (FSR_ER|FSR_BRK|FSR_FER|FSR_PER)
   54: 
   55: #define FCR_TFRST       0x0004
   56: #define FCR_RFRST       0x0002
   57: 
   58: #define LSR_ORER        0x0001
   59: 
   60: 
   61: EXPORT  void     tm_snd_dat( const UB* buf, INT size )
   62: {
   63:         _UH    d;
   64:         while(size--) {
   65: //              while(!(in_h(SCIFA_FSR) & FSR_TDFE)) ;      /* Waiting for FIFO space */
   66:                 do {
   67:                         d = in_h(SCIFA_FSR);
   68:                 } while(!(d&FSR_TDFE));
   69:                 out_b(SCIFA_FTDR, *buf++);
   70:                 and_h(SCIFA_FSR, ~(FSR_TEND|FSR_TDFE));
   71:         }
   72:         while(!(in_h(SCIFA_FSR) & FSR_TEND));          /* Waiting for transmission completion */
   73: }
   74: 
   75: EXPORT  void     tm_rcv_dat( UB* buf, INT size )
   76: {
   77:         while(size--) {
   78:                 while(!(in_h(SCIFA_FSR) & (FSR_RDF|FSR_DR))) {
   79:                         if((in_h(SCIFA_FSR) & FSR_ERROR) || (in_h(SCIFA_LSR) & LSR_ORER)) {
   80:                                 /* Clear error */
   81:                                 and_h(SCIFA_SCR, ~SCR_RE);  /* Stop receive */
   82:                                 or_h(SCIFA_FCR, FCR_RFRST); /* Reset FIFO */
   83:                                 and_h(SCIFA_FCR, ~FCR_RFRST);
   84:                                 and_h(SCIFA_FSR, ~FSR_ERROR);       /* Clear error bit */
   85:                                 and_h(SCIFA_LSR, ~LSR_ORER);        /* Clear overrun error */
   86:                                 or_h(SCIFA_SCR, SCR_RE);    /* Start receive */
   87:                         }
   88:                 }
   89:                 *buf++ = in_b(SCIFA_FRDR);            /* Read received data */
   90:                 and_h(SCIFA_FSR, ~(FSR_RDF|FSR_DR));  /* Clear RDF/DR */
   91:         }
   92:         return;
   93: }
   94: 
   95: EXPORT  void     tm_com_init(void)
   96: {
   97:         out_h(SCIFA_SCR, 0);                   /* Stop send/receive, Select internal clock */
   98:         out_h(SCIFA_FCR, FCR_RFRST|FCR_TFRST); /* Reset FIFO */
   99: 
  100:         and_h(SCIFA_FSR, ~(FSR_ER | FSR_BRK | FSR_DR));        /* Clear error bit */
  101:         and_h(SCIFA_LSR, ~LSR_ORER);                   /* Clear overrun error */
  102: 
  103:         /* Baud rate setting (115200bps) */
  104:         /* P1 clock=66.67MHz CKS=0 SCBRR=17 Bit rate error=0.46% => Baud rate=115200bps */
  105:         out_h(SCIFA_SMR, 0);                   /* UART mode, DATA=8bit, Parity=NONE, STOP=1, CLOCK=P1φ/1 (66.67MHz) */
  106:         out_b(SCIFA_SEMR, 0);                  /* Baud rate generator = normal mode, Operates with a frequency 16 times the transfer rate as the basic clock */
  107:         out_b(SCIFA_BRR, 17);                  /* Dividend ratio */
  108: 
  109:         out_h(SCIFA_FCR, 0x00000030);          /* Release FIFO reset */
  110:         or_h(SCIFA_SPTR, 0x00000003);          /* Break output settings */
  111:         out_h(SCIFA_SCR, (SCR_TE|SCR_RE));     /* Enable send/receive */
  112: 
  113:         return;
  114: }
  115: 
  116: #endif /* TM_COM_SERIAL_DEV */
  117: #endif /* IOTE_RZA2M */
  118: #endif /* USE_TMONITOR */