1: ==============================================================================
2: T-Kernel 2.0 (tef_em1d) Implementation Specifications
3: ==============================================================================
4: Version 1.00.00
5: 1. Overview
6:
7: This specifications describe the implementation that is specific to the
8: T-Engine reference board ("tef_em1d" hereafter) relating to T-Monitor,
9: T-Kernel, and device drivers.
10:
11: 2. Overall Implementation Specification
12:
13: 2.1 Register Name
14:
15: Most register names of the ARM processor follow the convention of
16: "ARM Architecture Reference Manual (ARMDDI 0406)". Especially,
17: the registers of the system control coprocessor may be represented
18: by the register specification in the form as shown below.
19:
20: CPn.CRn.opc1.CRm.opc2
21:
22: CPn Coprocessor number
23: CRn Coprocessor register specification
24: CRm Additional coprocessor register specification
25: opc1 Operation code 1
26: opc2 Operation code 2
27:
28: Some examples are given below:
29:
30: SCTLR (CP15.c1.0.c0.0) System control register
31: CPACR (CP15.c1.0.c0.2) Coprocessor access control register
32: TTBR0 (CP15.c2.0.c0.0) Translation table base register 0
33: TTBR1 (CP15.c2.0.c0.1) Translation table base register 1
34: TTBCR (CP15.c2.0.c0.2) Translation table base control register
35: PRRR (CP15.c10.0.c2.0) Primary region remap register
36: NMRR (CP15.c10.0.c2.1) Normal memory remap register
37:
38: 2.2 Processor Settings
39:
40: (1) MMU
41:
42: MMU shall have the following settings.
43: This settings should be set by T-Monitor at system startup and left
44: unchanged (must not be changed) thereafter.
45:
46: (a) SCTLR.AFE [29] = 1
47: Enables the access flag of the page table.
48:
49: (b) SCTLR.TRE [28] = 1
50: Enables the remap of the TEX memory attribute.
51:
52: (c) PRRR = 0x000a8aa4
53:
54: (d) NMRR = 0x44e048e0
55: Allocates the remap of the memory attributes as shown below.
56:
57: TEX[0] C B Memory type Internal cache External cache
58: 0 0 0 Strongly-order None None
59: 0 0 1 Device None None
60: 0 1 0 Normal WT-NA WT-NA
61: 0 1 1 Normal WB-NA WB-NA
62: 1 0 0 Normal None None
63: 1 0 1 Normal WT-NA WB-A
64: 1 1 0 (Not used)
65: 1 1 1 Normal WB-A WB-A
66:
67: WT-NA Write-through, no allocate on write
68: WB-NA Write-back, no allocate on write
69: WB-A Write-back, allocate on write
70:
71: (2) Security
72:
73: The processor shall always work in secure state. The system does not
74: use it in non-secure state (it never goes to non-secure state).
75: Therefore, the monitor mode of the ARM processor modes is not used.
76:
77: Various registers used in non-secure state are not specifically
78: initialized.
79:
80: 2.3 Memory Map
81:
82: (1) Overall
83:
84: Local address Mode
85: 0x00000000 +=======================+ ---
86: |Task space | | Virtual memory (Reserved)
87: 0x10000000 +=======================+ ---
88: |Peripheral device | D RW-
89: |(including unused area)|
90: 0x30000000 +-----------------------+
91: |RAM (64MB) | C RWX
92: |(including unused area)|
93: 0x40000000 +-----------------------+
94: |Peripheral device | D RW-
95: |(including unused area)| Physical address
96: 0x70000000 +-----------------------+ --- 0x00000000
97: |ROM (32MB) | C R-X | Mapping NOR Flash (*1)
98: 0x72000000 +-----------------------+ --- 0x02000000
99: |(Reserved) |
100: 0x80000000 +=======================+ ---
101: |Used for program map | |
102: 0x90000000 +-----------------------+ | Virtual memory (Reserved)
103: |Used for memory map | |
104: 0xa0000000 +=======================+ ---
105: |Built-in SRAM (128KB) | N RWX
106: |(including unused area)|
107: 0xb0000000 +-----------------------+
108: |Peripheral device | D RW-
109: |(including unused area)|
110: 0xd0000000 +=======================+ ---
111: |Shared memory space | | Virtual memory (Reserved)
112: 0xf0000000 +=======================+ ---
113: |Built-in Boot ROM | N R--
114: |(including unused area)|
115: 0xffffffff +-----------------------+
116:
117: Mode
118: Memory type/Cache attribute
119: C Cache ON Normal memory/Write-back cache, Write allocate
120: N Cache OFF Normal memory/Non-cacheable
121: D Device Device memory / Non-cacheable
122:
123: Access attribute ("-" means the attribute is turned off)
124: R Read enabled
125: W Write enabled
126: X Execution enabled
127:
128: - The areas specified as virtual memory are currently unused and
129: reserved.
130: The other areas are mapped as logical address = physical address,
131: and their mappings do not change dynamically.
132:
133: (*1) Note that the area for NOR Flash, which would be hidden in the
134: task space if logical address is set to physical address, is
135: not mapped as logical address = physical address but is mapped
136: by moving it as the memory map shown above. This mapping does not
137: change dynamically.
138:
139: Addresses in this specifications means logical addresses unless
140: otherwise stated.
141:
142: - At startup (initialization), the areas other than the virtual memory
143: are mapped by T-Monitor, and the MMU and caches are enabled.
144: The unused and virtual memory areas are not mapped and made
145: inaccessible.
146: The other areas are set as the modes shown in the above figure.
147: These mappings are performed in a section (in 1 MB units). Domains are
148: all set to 0. Any user level accesses are disabled.
149:
150: - The built-in SRAM and built-in Boot ROM are used at system startup
151: (at boot). After system startup, they are not used, and not managed
152: by OS. After system startup, the built-in SRAM can be used for any
153: application.
154:
155: (2) ROM details
156:
157: 0x70000000 +-----------------------+
158: |Exception branch processing |
159: |T-Monitor |
160: 0x70020000 +-----------------------+
161: |ROM information |
162: 0x70020080 +-----------------------+
163: |(Reserved) |
164: 0x70030000 +-----------------------+
165: |ROM disk | Not allocated in the initial state
166: 0x70030000 +-----------------------+
167: |T-Kernel |
168: +-----------------------+
169: |(User area) |
170: 0x72000000 +-----------------------+
171:
172: - The ROM disk area can be changed by setting the ROM information.
173:
174:
175: (3) RAM details
176:
177: 0x30000000 +-----------------------+
178: |1st level |
179: |page table |
180: 0x30004000 +-----------------------+
181: |Exception vector table |
182: 0x30004400 +-----------------------+
183: |System shared information |
184: 0x30004440 +-----------------------+
185: |T-Monitor |
186: |data/stack |
187: 0x30006000 +-----------------------+ <-- RAM_TOP
188: |Used by OS |
189: 0x34000000 +-----------------------+ <-- RAM_END
190:
191: - The following settings should be set by T-Monitor at system startup
192: and left unchanged (must not be changed) thereafter.
193:
194: VBAR (CP15.c12.0.c0.0) = 0x70000000 Vector base address register
195: TTBR1 (CP15.c2.0.c0.1) = 0x30000009 Translation table base register 1
196: TTBCR (CP15.c2.0.c0.2) = 0x00000004 Translation table base control
197: register
198:
199: Only the secure state registers are set, and the non-secure state ones
200: are not set. The vector base address register in the monitor mode,
201: MVBAR (CP15.c12.0.c0.1), is not set either.
202:
203: - RAM_TOP/RAM_END is managed and set in the system shared information by
204: T-Monitor.
205: The area between RAM_TOP and RAM_END is managed by OS. OS retrieves
206: these addresses from the system shared information.
207:
208: 2.4 Exception Vector Table
209:
210: Vector number
211: 0x30004000 +-----------------------+
212: |Default handler | 0
213: |Undefined instruction | 1
214: |Pre-fetch abort | 2
215: |Data abort | 3
216: 0x30004010 +-----------------------+
217: |Supervisor SVC 4 | 4
218: |call : | |
219: | SVC 28 | 28
220: 0x30004074 +-----------------------+
221: |Debug abort Instruction| 29
222: | data| 30
223: 0x3000407c +-----------------------+
224: |Fast interrupt FIQ | 31
225: 0x30004080 +-----------------------+
226: |Interrupt IRQ 0 | 32
227: | : | |
228: | IRQ 95 | 127
229: 0x30004200 +-----------------------+
230: |GPIO interrupt port 0 | 128
231: | : | |
232: | port 127| 255
233: 0x30004400 +-----------------------+
234:
235: - The default handler is called when an exception or interrupt occurs
236: with no handler registered. NULL means absence of registration.
237: - The vector number is used as the interrupt definition number (dintno)
238: of tk_def_int().
239: - The vector number is used as the SVC instruction number
240: (immediate value).
241: - IRQs 0 to 95 correspond to INTs 0 to 95 of the interrupt controller
242: (AINT).
243:
244: 2.5 ROM Information
245:
246: typedef struct {
247: FP kernel; /* OS start address */
248: UB *sysconf; /* Top of SYSCONF */
249: UB *devconf; /* Top of DEVCONF */
250: void *userarea; /* Top of RAM user area */
251: FP userinit; /* User initialization program address */
252: FP resetinit; /* Reset initialization program address */
253: VW rsv[10]; /* Reserved (always 0) */
254: UW rd_type; /* ROM disk kind */
255: UW rd_blksz; /* ROM disk block size */
256: UW rd_saddr; /* ROM disk start address */
257: UW rd_eaddr; /* ROM disk end address */
258: VW rsv2[12]; /* Reserved (always 0) */
259: } RomInfo;
260:
261: kernel Specifies the T-Kernel start address.
262: T-Monitor starts OS by jumping to this address.
263: Use NULL when T-Kernel is not stored in ROM.
264:
265: sysconf Specifies the address of ROM in which SYSCONF is stored.
266: Use NULL when this is not stored in ROM.
267:
268: devconf Specifies the address of ROM in which DEVCONF is stored.
269: Use NULL when this is not stored in ROM.
270:
271: userarea Specifies the top address of the user area in RAM that
272: is excluded from the OS management. Normally specifies
273: the end of the RAM reserved area, 0x40000000.
274: The lower value of this address and the end
275: (upper) address of the actual RAM area is used as RAM_END.
276:
277: userinit Specifies the entry address of the initialization
278: program created by the user.
279: After OS starts, the program registered here is
280: executed.
281: When NULL is specified, no user initialization program
282: is executed.
283: NULL is usually specified since the user
284: initialization program is not required generally.
285:
286: resetinit Specifies the entry address of the reset initialization
287: program created by the user.
288: After the reset is processed, the program registered
289: here is executed.
290: When NULL is specified, no reset initialization program
291: is executed.
292: This is specified when the hardware initialization
293: processing for the extended board, etc. is needed before
294: starting OS.
295:
296: rd_xxxx specifies the ROM disk in ROM. If it does not exist, set all to 0.
297:
298: rd_type Disk type (1 : ROM disk (write-protect))
299: rd_blksz Disk block size (normally 512)
300: rd_saddr Start address of ROM disk area
301: rd_eaddr End address of ROM disk area (+1)
302:
303: 2.6 System Shared Information
304:
305: typedef struct {
306: (*2) void *ramtop; /* Top of RAM free space (RAM_TOP) */
307: (*2) void *ramend; /* End of RAM free space (+1) (RAM_END) */
308: UB *sysconf; /* Top of SYSCONF */
309: UB *devconf; /* Top of DEVCONF */
310: W taskindp; /* Task-independent portion flag */
311: UW taskmode; /* Task mode flag */
312: VW osrsv[4]; /* Used by OS */
313: VW rsv[6]; /* Reserved */
314: } SysCommonInfo;
315:
316: (*2) means the information set in T-Monitor.
317:
318: taskindp Is used as the task-independent portion flag by T-Kernel/OS.
319: = 0 : Task portion
320: > 0 : Task-independent portion
321:
322: taskmode Is used as the task mode flag by T-Kernel/OS.
323:
324: 31 18 17 16 15 2 1 0
325: +---------+-----+---------+-----+
326: | Reserved (0) | PPL | Reserved (0) | CPL |
327: +---------+-----+---------+-----+
328: CPL Current protection level
329: PPL Previous protection level
330:
331: (1) T-Monitor
332:
333: Initializes the system shared information at system startup and boot start.
334:
335: ramtop, ramend
336: Specifies the top address and end addresses of the RAM free space.
337: ( ramend - ramtop ) is the size of the free space.
338:
339: Clears all the other system shared information to 0.
340:
341: (2) T-Kernel startup processing
342:
343: At the beginning of the startup processing, the following set up is performed:
344:
345: sysconf address of SYSCONF retrieved from the ROM information
346: devconf address of DEVCONF retrieved from the ROM information
347: ramtop address of RAM, excluding the area consumed as the
348: data area of T-Kernel
349:
350: 2.7 System Configuration Definition (SYSCONF)
351:
352: The stack size (in bytes) for each exception mode is specified in SYSCONF.
353: These stacks for the exception modes do not need a large space since they
354: are usually used only for the entry and exit of the handler.
355:
356: Normal setting value
357: AbtStkSz 64 # Abort (MMU)
358: UndStkSz 64 # Undefined instruction exception
359: IrqStkSz 512 # Interrupt (IRQ)
360: FiqStkSz 128 # Fast interrupt (FIQ)
361:
362: These stacks are allocated by OS. The supervisor (SVC) stack is not
363: specified here since it is a system stack.
364:
365: T-Monitor does not use these stacks. T-Monitor uses its own stack
366: internally.
367:
368: At startup (initialization), T-Monitor sets a stack area with a
369: minimum size of 4 words, which is used for the exception branch
370: processing, for each stack pointer R13 in the exception modes.
371: These stacks are used only before OS starts up.
372:
373: 2.8 Supervisor Call Allocation
374:
375: SVC 4 T-Monitor service call (T-Monitor)
376: SVC 5 Reserved
377: SVC 6 T-Kernel system call or extended SVC (T-Kernel)
378: SVC 7 tk_ret_int() system call (T-Kernel)
379: SVC 8 Task dispatcher (T-Kernel)
380: SVC 9 Debugger support function (T-Kernel)
381: SVC 10 Return from task exception (T-Kernel)
382: SVC 11 Process kill termination request (Extension)
383: SVC 12 to 27 Reserved
384:
385: 2.9 Protection Level
386:
387: Protection Level Processor mode
388: 0 SVC: Supervisor mode, and all the modes other than USR and SYS
389: 1 SYS: System mode
390: 2 SYS: System mode
391: 3 USR: User mode
392:
393: In system mode (SYS), there is no practical difference between
394: protection levels 1 and 2. There is no difference between protection
395: levels by MMU because there are only two levels, privileged and user,
396: in the memory protection by MMU, and all of the protection levels 0 to 2
397: result in privileged mode.
398:
399: 2.10 Stack
400:
401: (1) User stack/system stack
402:
403: The user mode (USR) and system mode (SYS) stacks are used as
404: user stack, and the supervisor mode (SVC) stack is used as
405: system stack.
406:
407: User stack R13_usr
408: System stack R13_svc
409:
410: (2) Interrupt stack
411:
412: In addition to the user stack/system stack, there is the interrupt stack
413: independent of tasks. A stack in any exception mode other than the
414: supervisor mode (SVC) is called as interrupt stack. A separate
415: stack area is allocated to such a stack.
416:
417: Interrupt stack R13_abt, R13_und, R13_irq, R13_fiq
418:
419: 2.11 Exception/Interrupt Handler
420:
421: The exception branch processing routine is provided for jumping to
422: each handler by referring to the vector table. Except for fast interrupt
423: (FIQ), this branch routine sets information in registers and stacks
424: before jumping to each handler. The set values varies depending on the
425: exception. However, in the ip (R12) register, a vector table address
426: that is common to all the exceptions is set. By this vector table
427: address, the vector number for a raised exception can be identified.
428:
429: (ip - 0x30004000 ) / 4 = Vector number
430:
431: When the control is transfered to the default handler, ip represents the
432: vector table address for the raised exception rather than one for the
433: default handler.
434:
435: The jump to the exception handler is performed with the
436: interrupt-disabled state (CPSR.I,F,A keep their states immediately after
437: the exception occurs). If the least significant bit of the handler
438: address in the vector table is 1, switching to Thumb mode occurs
439: because the BX instruction is used to jump to the exception handler.
440: Otherwise, switching doesn't occur, and ARM mode continues.
441:
442: In the branch routine, some registers are used for the branch
443: processing. These registers are saved in the stack as shown below.
444: Since the branch routine does not save other registers in the stack,
445: they should be saved by handlers if necessary. When the control returns
446: from the handler, saved registers should be restored, and these registers
447: must include the registers saved by the branch routine.
448:
449: (1) Fast interrupt (FIQ)
450:
451: The handler set in the FIQ interrupt vector is unconditionally called.
452: Rather than a separate vector for each factor causing interrupts,
453: the common handler is called for every cause.
454: No default handler is ever called. Therefore, when using FIQ interrupt,
455: you must define a handler.
456:
457: No registers are saved when a handler is called.
458: The content of R12_fiq register is destroyed since it is used for
459: calling a handler.
460:
461: Processor state when a handler is called
462: CPSR.F = 1 Fast interrupt disabled
463: CPSR.I = 1 Interrupt disabled
464: CPSR.A = 1 Abort exception disabled
465: CPSR.M = 17 FIQ: Fast interrupt mode
466:
467: (2) Interrupt (IRQ)
468:
469: A handler is called by determining the interrupt priority from the
470: interrupt factor retrieved from the ACPU interrupt mask status register
471: (IT0_MST0,1,2) of the interrupt controller (AINT) and branching to the
472: handler with the highest priority.
473: The interrupt priorities are arranged in descending order of the
474: interrupt factor numbers (INT 0 to 95). INT 95 (IRQ95) has the highest
475: priority, and INT 0 (IRQ0) has the lowest priority.
476: When interrupt factors do not exist, the handler for INT 95 (IRQ95) is
477: called.
478:
479: For the GPIO interrupt (shown below), a further branching is done
480: using the interrupt factor from the GPIO port.
481:
482: IRQ26 GIO6 Interrupt (GPIO port from 96 to 111)
483: IRQ27 GIO7 Interrupt (GPIO port from 112 to 127)
484: IRQ50 GIO0 Interrupt (GPIO port from 0 to 15)
485: IRQ51 GIO1 Interrupt (GPIO port from 16 to 31)
486: IRQ52 GIO2 Interrupt (GPIO port from 32 to 47)
487: IRQ53 GIO3 Interrupt (GPIO port from 48 to 63)
488: IRQ79 GIO4 Interrupt (GPIO port from 64 to 79)
489: IRQ80 GIO5 Interrupt (GPIO port from 80 to 95)
490:
491: A handler is called by determining the interrupt priority by the
492: interrupt factor retrieved from the input port interrupt maskable status
493: register (GIO_MST) and branching to the handler with the highest priority.
494: The interrupt priorities are arranged in descending order of the input
495: port numbers (port 0 to 127). The port 127 has the highest priority, and
496: the port 0 has the lowest priority. Since the GPIO interrupts are
497: divided into 16-port groups as shown above, the priority is determined
498: within each group.
499: When interrupt factors do not exist, the handler for IRQ95 is called.
500: Note that the GPIO setting determines whether or not each port of
501: GPIO is used to cause interrupt.
502:
503: Stack when a hander is called
504: +---------------+
505: sp -> |R3 |
506: |R12=ip |
507: |R14=lr | <- Return address from interrupt
508: |SPSR |
509: +---------------+
510:
511: Registers when a handler is called
512: ip = Vector table address
513: lr, r3 = Undefined
514:
515: Processor state when a handler is called
516: CPSR.F = ? Remains as when being interrupted
517: CPSR.I = 1 Interrupt disabled
518: CPSR.A = 1 Abort exception disabled
519: CPSR.M = 18 IRQ: Interrupt mode
520:
521: (3) Other exceptions (SVC,ABT,UND)
522:
523: Stack when a handler is called
524: +---------------+
525: sp -> |R12=ip |
526: |R14=lr | <- Return address
527: |SPSR |
528: +---------------+
529:
530: Return address
531: SVC address of the following instruction that follows the SVC instruction
532: ABT address of the aborted instruction
533: UND address of the instruction that follows the undefined isntruction
534:
535: Registers when a handler is called
536: ip = Vector table address
537: lr = Undefined
538:
539: Processor state
540: CPSR.F = ? Remains as when exception occurs
541: CPSR.I = 1 Interrupt disabled
542: CPSR.A = ? SVC,UND: Remains as when exception occurs
543: 1 ABT: Abort exception disabled
544: CPSR.M = 19 SVC: Supervisor mode
545: 23 ABT: Abort mode
546: 27 UND: Undefined instruction exception mode
547:
548: (a) Abort exception (ABT)
549:
550: For the pre-fetch abort and data abort, if a debug event is represented
551: by the fault status register (IFSR,DFSR), the debug abort
552: (instruction or data) handler is called.
553: Otherwise, the pre-fetch abort or data abort handler is called.
554:
555: 2.12 System Call
556:
557: The convention for register saving and argument passing comply with
558: that of the C language function call.
559: Basic register assignment in C language program is as follows:
560:
561: R0 to R3, R12 = ip temporary registers
562: R4 to R10 permanent registers
563: R11 = fp frame pointer
564: R13 = sp stack pointer
565: R14 = lr link register (Function return address)
566: R15 = pc program counter
567:
568: Arguments R0 to R3
569: Return code R0
570:
571: Temporary registers are destroyed by a function call. Other registers
572: are saved.
573: Stack is managed using the FD (Full Descending) method.
574:
575: Before executing the SVC instruction in a mode other than USR (User mode)
576: and SYS (System mode), the R14_svc register must be saved in advance
577: because its content is destroyed by SVC instruction.
578: In principle, the SVC instruction can be used in the following modes:
579:
580: USR: User mode
581: SYS: System mode
582: SVC: Supervisor mode
583:
584: The SVC instruction needs to be executed as follows:
585:
586: stmfd sp!, {lr}
587: svc #
588: ldmfd sp!, {lr}
589:
590: For USR and SYS modes, lr does not need to be saved, but in order to call
591: the SVC instruction in the same uniform manner irrespective of modes,
592: the above calling sequence shall be used normally.
593:
594: If the SVC instruction is used in a mode other than USR, SYS, and SVC
595: modes, R14_svc needs to be saved using whatever method selected.
596:
597: (1) T-Monitor service call
598:
599: R12=ip function codes
600: R0 first argument
601: R1 second argument
602: R2 third argument
603: R3 fourth argument
604: SVC 4
605: R0 return code
606:
607: Up to four arguments can be used.
608: The T-Monitor service call is invoked by SVC 4 with the arguments and
609: function code set in registers as shown above.
610:
611: (2) T-Kernel system call
612:
613: R12=ip Function code (< 0)
614: R0 first argument
615: R1 second argument
616: R2 third argument
617: R3 fourth argument
618: R4 pointer to the area where fifth and subsequent arguments are
619: saved
620: fifth and subsequent arguments use the stack
621: +---------------+
622: R4 -> |Fifth argument |
623: +---------------+
624: SVC 6
625: R0 return code
626:
627: Fourth and preceding arguments are set in the registers, and fifth and
628: latter arguments are pushed on the stack. Then T-Kernel system call is
629: invoked by using SVC 6.
630:
631: T-Kernel/DS system calls are handled similarly, but SVC 9 is used instead.
632:
633: (3) Extended SVC
634:
635: R12=ip function code ( >= 0)
636: R0 pointer to the argument packet
637: SVC 6
638: R0 return code
639:
640: All arguments are stored in a packet, and the address of the packet is
641: set in the R0 register. Then the extended SVC is invoked by using SVC 6.
642: The packet is usually created on the stack but may be created in another
643: place. The number and type of arguments are not limited since they are
644: inside a packet.
645:
646: 2.13 Boot
647:
648: Startup is done in the following steps.:
649:
650: 1. T-Monitor initializes hardware.
651: 2. T-Monitor initializes the exception vector table and system shared
652: information.
653: 3. T-Monitor jumps to the OS startup address specified by `kernel' in
654: the ROM information to transfer the control to OS and start the system.
655:
656: (1) T-Monitor boot processing
657:
658: (a) Exception vector table setting
659:
660: The following vectors are set so that T-Monitor itself can process them.
661: Other vectors are set to NULL so that the default handler will be started.
662:
663: Vector number
664: 0 Default handler
665: 4 T-Monitor service call (SVC 4)
666: 29 Debug abort (Instruction)
667: 30 Debug abort (Data)
668: 136 Abort switch (SW1) (GPIO port 8)
669:
670: 58 GIO6: GPIO interrupt branch processing (IRQ26)
671: 59 GIO7: GPIO interrupt branch processing (IRQ27)
672: 82 GIO0: GPIO interrupt branch processing (IRQ50)
673: 83 GIO1: GPIO interrupt branch processing (IRQ51)
674: 84 GIO2: GPIO interrupt branch processing (IRQ52)
675: 85 GIO3: GPIO interrupt branch processing (IRQ53)
676: 111 GIO4: GPIO interrupt branch processing (IRQ79)
677: 112 GIO5: GPIO interrupt branch processing (IRQ80)
678:
679: The default handler displays the exception information and then displays
680: the T-Monitor prompt to wait for a command input.
681:
682: (b) OS startup
683:
684: OS can be started up by referring to the OS startup address stored in
685: `kernel' in the ROM information and jumping to the address if the
686: address is not NULL.
687: If the OS startup address is NULL, ROM startup is not done, and
688: T-Monitor waits for a command input.
689:
690: When the control is transferred to OS, the CPU state is as follows and
691: allows T-Monitor service calls.
692:
693: CPSR.I = 1 Interrupt disabled
694: CPSR.F = 1 Fast interrupt disabled
695: CPSR.A = 0 Abort exception enabled
696: CPSR.T = 0 ARM mode
697: CPSR.M = 19 SVC: Supervisor mode
698: R13_svc (sp) Monitor stack
699: R0 0 (indicates ROM startup)
700: Other general registers are undefined
701:
702: Cache memory
703: - Cache is turned off (SCTLR.C=0, I=0, Z=0)
704: - All the cache content is invalid
705:
706: The stack pointer, R13_svc (sp) points the T-Monitor stack area
707: (Monitor stack). During OS startup, this monitor stack is used.
708: The T-Monitor service call is invoked while sp points to the Monitor
709: stack. Note that the Monitor stack used by the OS startup shall be
710: 2 KB or less.
711:
712: 2.14 User Initialization Program
713:
714: The user initialization program is a user-defined routine located on
715: ROM to start or end a user-created program, etc. The user initialization
716: program is called from the initialization startup task in the following
717: format:
718:
719: INT userinit( INT ac, UB **av )
720:
721: ac = 0 at system startup
722: = -1 at system end
723:
724: return code 1 start usermain
725: 0 system shutdown (Power off)
726: -1 reset (Restart)
727:
728: At system startup, it is called with ac = 0. At system end, it is
729: called with ac = -1. In the call at end (ac = -1), return code is
730: ignored.
731: It is processed as follows:
732:
733: fin = userinit(0, NULL);
734: if ( fin > 0 ){
735: fin = usermain();
736: }
737: userinit(-1, NULL);
738:
739: The user initialization program is executed in the context of the
740: initialization startup task. The task priority is 138. The stack
741: consumption by the user initialization program shall be 4 KB or less.
742:
743: There are two options after startup processing of the user program.
744: (A) Wait for the end of the user program, and then retur from
745: userinit().
746: (B) Return from userinit() without waiting for the end of the user
747: program.
748:
749: In either case, the next processing can be selected by the return code
750: from userinit().
751:
752: 2.15 Reset Initialization Program
753:
754: The reset initialization program is a user-defined routine inside
755: ROM to initialize hardware such as the extended board immediately after
756: reset. The reset initialization program is called at the end of reset
757: processing by T-Monitor in the following format:
758:
759: void resetinit( void )
760:
761: The stack consumption by the reset initialization program shall be 2 KB
762: or less.
763:
764: 2.16 Exception/Interrupt Handler Entry Routine
765:
766: Please see the following files:
767:
768: monitor/hwdepend/tef_em1d/src/eitent.S
769: include/tk/sysdepend/tef_em1d/sysdef_depend.h
770: include/tk/sysdepend/tef_em1d/asm_depend.h
771:
772: 3. T-Monitor Implementation Specification
773:
774: 3.1 Register Command
775:
776: The register command supports the following registers:
777:
778: (a) General registers (G)
779:
780: R0, R1, R2, R3, R4, R5, R6, R7,
781: R8, R9, R10/SL, R11/FP, R12/IP, R13/SP, R14/LR, R15/PC
782: R8_USR, R9_USR, R10_USR, R11_USR, R12_USR, R13_USR, R14_USR
783: R8_FIQ, R9_FIQ, R10_FIQ, R11_FIQ, R12_FIQ, R13_FIQ, R14_FIQ
784: R13_IRQ, R14_IRQ
785: R13_SVC, R14_SVC
786: R13_ABT, R14_ABT
787: R13_UND, R14_UND
788:
789: * The monitor mode registers (R13_MON, R14_MON) are not supported
790:
791: (b) Control/System registers (C)
792:
793: CPSR, SPSR
794: SPSR_FIQ, SPSR_IRQ, SPSR_SVC, SPSR_ABT, SPSR_UND
795: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, CTXIDR
796:
797: * The following system control coprocessor registers
798: (CP15.CRn.opc1.CRm.opc2) are supported:
799:
800: SCTLR (CP15.c1.0.c0.0) System control register
801: TTBR0 (CP15.c2.0.c0.0) Translation table base register 0
802: TTBR1 (CP15.c2.0.c0.1) Translation table base register 1
803: TTBCR (CP15.c2.0.c0.2) Translation table base control register
804: DACR (CP15.c3.0.c0.0) Domain access control register
805: DFSR (CP15.c5.0.c0.0) Data fault status register
806: IFSR (CP15.c5.0.c0.1) Instruction fault status register
807: DFAR (CP15.c6.0.c0.0) Data fault address register
808: IFAR (CP15.c6.0.c0.2) Instruction fault address register
809: CTXIDR (CP15.c13.0.c0.1) Context ID register
810:
811: * The monitor mode register (SPSR_MON) is not supported
812:
813: 3.2 Break Point Command
814:
815: The following break attribute is supported:
816:
817: S : Software breakpoints
818: Breaks immediately before executing the instruction at
819: <break address>.
820:
821: - Up to 8 software breakpoints
822: - Breakpoint setting at the odd address is assumed to be Thumb
823: instruction. Note that Thumb-2 instruction is not supported.
824: - If ICE is connected, the breakpoint operation is not guaranteed
825:
826: 3.3 Trace (Step/Next) Command
827:
828: All the breakpoints are disabled during trace execution.
829: If SVC instruction is encountered during trace execution, destination of
830: SVC is not traced.
831: The next instruction to be executed is not disassembled, and memory dump
832: is displayed, instead.
833:
834: 3.4 Back Trace, Disassemble Command
835:
836: Not supported.
837:
838: 3.5 Disk Command
839:
840: This cannot be used since the disk device is not supported.
841:
842: 3.6 Kill Command
843:
844: This terminates the monitor and executes SVC 11.
845: Nothing is done when the SVC 11 handler is not set.
846:
847: - Handler for SVC11 is assumed to be set in the T-Kernel Extension.
848:
849: * Kill command forcibly terminates a process from T-Monitor.
850: A process is implemented in T-Kernel Extension. Hence the
851: processing to kill a process is performed inside a handler within
852: T-Kernel Extension.
853:
854: 3.7 WriteROM Command
855:
856: Content on RAM can be written to NOR Flash ROM by using the following
857: WriteROM command:
858:
859: WriteROM(WROM) rom_addr, data_ram_addr, block_count : Write Flash ROM
860: blocks
861: rom_addr : 0x70000000 - 0x71FE0000
862: data_ram_addr : 0x30020000 - 0x33FE0000
863: block_count : 1 - 0x100 (1 block = 128KB)
864:
865: - Writing is done in 128 KB blocks, and the Flash ROM address must be at
866: 128 KB boundary.
867: - If T-Monitor area (0x70000000 to 0x7001FFFF) is specified,
868: message is displayed for confirmation, the system is reset and
869: restarted after rewriting.
870:
871: 3.8 FlashLoad Command
872:
873: S-Format data can be loaded and written to NOR Flash ROM by using the
874: following FlashLoad command:
875:
876: FlashLoad(FLLO) [attr] : Load S-Format Data & Write Flash ROM
877: attr: X Use XMODEM protocol
878: E Fill write blocks with 0xFF
879: Default : Overwrite original Flash ROM Image
880:
881: - If X is specified, S-Format data load is done using XMODEM protocol.
882: Otherwise, it is done without high-level protocol.
883: - If E is specified, 0xFF is written to the non-loaded portion in the
884: 128 KB block. Otherwise, the non-loaded portion remains unchanged.
885:
886: 3.9 DIP Switch
887:
888: OFF ON
889: --------------------------------------------------------------------
890: SW-1 BOOTSEL0 OFF -
891: SW-2 BOOTSEL1 OFF -
892: SW-3 BOOTSEL2 OFF -
893: SW-4 Startup selection Automatic boot Monitor startup
894:
895: SW-4 selects automatic boot (OS startup) with OFF, and monitor startup
896: without boot with ON.
897:
898: The other switches must be set as shown above.
899:
900: 3.10 Search Order of Device to Be Started Up
901:
902: When starting with the DIP switch SW-4 set to ON, T-Monitor is started
903: up.
904: When SW-4 is set to OFF, a program (RomInfo.kernel) on ROM is started up
905: if it is set, or T-Monitor is started up otherwise.
906:
907: 3.11 Console
908:
909: UART0 is used as the serial port for the T-Monitor console.
910: The communication parameters are as follows:
911:
912: Baud rate 115,200 bps
913: Data length 8 bit
914: Stop bit 1 bit
915: Parity None
916: Flow control XON/XOFF
917:
918: 3.12 T-Monitor Service Call
919:
920: The convention for register saving and argument passing comply with
921: that of the C language function call.
922: Up to four arguments can be used.
923:
924: T-Monitor service call is invoked by SVC 4 with the function code
925: set in R12/IP.
926:
927: All interrupts are masked during the service call execution. The
928: dedicated stack area in T-Monitor is used as the stack.
929:
930: R12/IP Function codes
931: R0 first argument
932: R1 second argument
933: R2 third argument
934: R3 fourth argument
935: SVC 4
936: R0 return code
937:
938: Function codes
939: 0 Enter T-Monitor Enter the monitor
940: 1 Get Character Input 1 character from console
941: 2 Put Character Output 1 character to console
942: 3 Get Line Input 1 line from console
943: 4 Put String Output string to console
944: 5 Execute Command Execute monitor command
945: 6 (Reserved)
946: 7 (Reserved)
947: 8 (Reserved)
948: 9 System Exit System exit
949: 255 Extension SVC Extended service function
950:
951: 3.13 T-Monitor Extended Service Call
952:
953: tm_extsvc(INT fno, INT p1, INT p2, INT p3)
954:
955: fno Function
956: -----------------------------------------------------------------
957: 0x00 Retrieve baud rate at debug port
958: p1 to p3: Not used
959: Return value: 115200
960:
961: 0x01 Retrieve ROM disk information
962: p1: Area to store the ROM disk information pointer
963: p2 to p3: Not used
964: Return value: 0: OK, < 0: Error
965:
966: The following addresses on ROM are stored at p1:
967:
968: p1 --> UW rd_type; /* ROM disk kind */
969: UW rd_blksz; /* ROM disk block size */
970: UW rd_saddr; /* ROM disk start address */
971: UW rd_eaddr; /* ROM disk end address */
972:
973: 0x04 (Reserved)
974:
975: 0x10 Retrieve DIP SW state
976: p1 to p3: Not used
977: Return value: bit 0 to 4 : Undefined
978: bit 5 : SW-4 Startup selection (0: OFF 1: ON)
979: bit 6 to 31 : Undefined
980:
981: 0x11 (Reserved)
982:
983: 0x20 Write to NOR Flash ROM
984: p1: Flash ROM address (Written destination)
985: 0x7###0000, ### = 000 - 1FE
986: p2: RAM address (Written data)
987: 0x3###0000, ### = 002 - 3FE
988: p3: Number of written blocks (1 block = 128 KB)
989: 0x01 to 0x100
990: Return value: 0: OK, < 0 Error
991:
992: - Writing is done in 128 KB blocks, and the Flash ROM address
993: must be at 128 KB boundary.
994: - If T-Monitor area (0x70000000 to 0x7001FFFF) is specified,
995: message is displayed for confirmation, the system is
996: reset and restarted after rewriting.
997:
998: 3.14 Clock Initialization
999:
1000: T-Monitor sets the following ASMU registers for EM1-D512 at
1001: startup:
1002:
1003: Register Setting value
1004: AUTO_FRQ_CHANGE 0x00000000
1005: PLL1CTRL0 0x00000079
1006: PLL1CTRL1 0x00000000
1007: PLL2CTRL0 0x00000061
1008: PLL2CTRL1 0x00000000
1009: CLK_MODE_SEL 0x00000001
1010: NORMALA_DIV 0x00244200
1011: DIVU70SCLK 0x00000000
1012: DIVU71SCLK 0x00000000
1013: DIVU72SCLK 0x00000000
1014: DIVLCDLCLK 0x00000004
1015: DIVIICSCLK 0x00530053
1016: DIVTIMTIN 0x00000003
1017: DIVSP0SCLK 0x00000074
1018: TI0TIN_SEL 0x00000000
1019: TI1TIN_SEL 0x00000000
1020: TI2TIN_SEL 0x00000000
1021: TI3TIN_SEL 0x00000000
1022: TIGnTIN_SEL 0x00000000
1023: AHBCLKCTRL0 0x00000000
1024: AHBCLKCTRL1 0x00000000
1025: APBCLKCTRL0 0x00000000
1026: APBCLKCTRL1 0x00000000
1027: CLKCTRL 0x00000000
1028: GCLKCTRL0ENA 0xffffffff (0x00000000 after GCLKCTRL0 is set)
1029: GCLKCTRL0 0xffffffff
1030: GCLKCTRL1ENA 0xffffffff (0x00000000 after GCLKCTRL1 is set)
1031: GCLKCTRL1 0xffffffff
1032: GCLKCTRL2ENA 0xffffffff (0x00000000 after GCLKCTRL2 is set)
1033: GCLKCTRL2 0xffffffff
1034: GCLKCTRL3ENA 0xffffffff (0x00000000 after GCLKCTRL3 is set)
1035: GCLKCTRL3 0xffffffff
1036: RESETREQ0ENA 0xffffffff (0x00000000 after RESETREQ0 is set)
1037: RESETREQ0 0xffffffe7
1038: RESETREQ1ENA 0xffffffff (0x00000000 after RESETREQ1 is set)
1039: RESETREQ1 0xffffffff
1040: RESETREQ2ENA 0xffffffff (0x00000000 after RESETREQ2 is set)
1041: RESETREQ2 0xffffffff
1042: RESETREQ3ENA 0xffffffff (0x00000000 after RESETREQ3 is set)
1043: RESETREQ3 0xffffffff
1044:
1045: These values result in the clocks as follows. Clocks
1046: are supplied for all the modules, and all the reset state of modules
1047: other than DSP are released.
1048:
1049: PLL1: 499.712 MHz
1050: ACPU: PLL1/1 499.712 MHz
1051: ADSP: PLL1/1 499.712 MHz
1052: HBUS: PLL1/3 166.571 MHz
1053: LBUS: PLL1/6 83.285 MHz
1054: FLASH: PLL1/6 83.285 MHz
1055: MEMC: PLL1/3 166.571 MHz
1056:
1057: PLL2: 401.408 MHz
1058: LCD_LCLK: PLL2/16 25.088 MHz
1059:
1060: PLL3: 229.376 MHz
1061: U70_SCLK: PLL3/1 229.376 MHz
1062: U71_SCLK: PLL3/1 229.376 MHz
1063: U72_SCLK: PLL3/1 229.376 MHz
1064: Txx_TIN: PLL3/8 28.672 MHz
1065: IIC_SCLK: PLL3/48 4.779 MHz
1066: SP0_SCLK: PLL3/128 1.792MHz
1067:
1068: The clock always operates in Normal Mode A, other modes are not supported.
1069: Automatic frequency switch function is not used, and is not supported.
1070:
1071: Device drivers should handle the module power, reset operation, and
1072: clock divide ratio and clock gate used by the modules on their own
1073: if necessary.
1074:
1075: 3.15 Pin Multiplexer Initialization
1076:
1077: T-Monitor sets the following pin multiplexers for EM1-D512 at startup:
1078:
1079: Register Setting value
1080: CHG_L1_HOLD 0x00000000
1081: CHG_CTRL_AB0_BOOT 0x00000001
1082: CHG_PINSEL_G0 0x55400C00
1083: CHG_PINSEL_G16 0x55555555
1084: CHG_PINSEL_G32 0x54555055
1085: CHG_PINSEL_G48 0x55555555
1086: CHG_PINSEL_G64 0xffc05555
1087: CHG_PINSEL_G80 0x06556940
1088: CHG_PINSEL_G96 0x55555555
1089: CHG_PINSEL_G112 0x00000555
1090: CHG_PINSEL_SP0 0x00000000
1091: CHG_PINSEL_DTV 0x00000001
1092: CHG_PINSEL_SD0 0x00000000
1093: CHG_PINSEL_SD1 0x00000002
1094: CHG_PINSEL_IIC2 0x00000000
1095: CHG_PULL_G0 0x55055005
1096: CHG_PULL_G8 0x00000005
1097: CHG_PULL_G16 0x00000000
1098: CHG_PULL_G24 0x00000000
1099: CHG_PULL_G32 0x00550000
1100: CHG_PULL_G40 0x00050000
1101: CHG_PULL_G48 0x11111111
1102: CHG_PULL_G56 0x11111111
1103: CHG_PULL_G64 0x11111111
1104: CHG_PULL_G72 0x00000005
1105: CHG_PULL_G80 0x00400050
1106: CHG_PULL_G88 0x55000444
1107: CHG_PULL_G96 0x44444444
1108: CHG_PULL_G104 0x04044444
1109: CHG_PULL_G112 0x00000000
1110: CHG_PULL_G120 0x00000000
1111: CHG_PULL0 0x50000004
1112: CHG_PULL1 0x15110600
1113: CHG_PULL2 0x60000661
1114: CHG_PULL3 0x00000000
1115: GIO_E0_L 0x000001d9
1116: GIO_E1_L 0x00000604
1117: GIO_E0_H 0x00001030
1118: GIO_E1_H 0x00000000
1119: GIO_E0_HH 0xc0020100
1120: GIO_E1_HH 0x00040200
1121: GIO_OL_L 0x06040000
1122: GIO_OL_HH 0x02000000
1123: GIO_OH_HH 0x00040000
1124:
1125: These result in the pin settings that support the following modules:
1126:
1127: AB0(AsyncBus0)
1128: LCD
1129: SD0
1130: PM0
1131: UART0, UART1
1132: IIC
1133: USB
1134: GPIO
1135: P0 In DA9052(nIRQ)
1136: P2 Out/0 ML7037(/PDN)
1137: P3 In microSD(CD)
1138: P4 In Push-SW(SW4)
1139: P6 In Push-SW(SW3)
1140: P7 In Push-SW(SW2)
1141: P8 In Push-SW(SW1)
1142: P9 Out/0 ML7037(PDN)
1143: P10 Out/0 Camera module (STBY)
1144: P36 In MKY36(/INT0)
1145: P37 In MKY36(/INT1)
1146: P44 In LAN9221(IRQ)
1147: P72 In MAX7324(/INT)
1148: P73 Out/0 LM4876(/SHUTDOWN)
1149: P81 In LAN9221(PME)
1150: P82 Out/0 LCD
1151: P94 In RTC(/TIRQ)
1152: P95 In RTC(/AIRQ)
1153:
1154: 3.16 LED Operation and Retrieval of DIP Switch State
1155:
1156: To operate LEDs 5 to 8 and to retrieve the state of the DIP switch SW-4,
1157: IIC2 and port expander (MAX7324) connected to them are used.
1158:
1159: Although photocouplers are connected to the port expander besides LEDs,
1160: they are not handled by T-Monitor.
1161:
1162: 4. T-Kernel Implementation Specification
1163:
1164: 4.1 Use Thumb Instruction Set
1165:
1166: To use the Thumb instruction set, the code must be programmed according
1167: to "ARM/Thumb Interworking".
1168: For C language programs, you need to specify the -mthumb-interwork -mthumb
1169: option at compile time.
1170:
1171: To specify the code written in the Thumb instruction set to run as a
1172: task or handler, set the least significant bit of the address to 1. When
1173: the ARM instruction set is used, set it to 0. It is usually set by the
1174: linker automatically, and you do not have to be concerned about it.
1175:
1176: 4.2 Determination of System State
1177:
1178: (1) Task-independent portion
1179: (exception, interrupt handler, time event handler)
1180:
1181: Use the taskindp flag in the system shared information (SysCommonInfo)
1182: to judge for it.
1183:
1184: taskindp = 0 Task portion
1185: taskindp > 0 Task-independent portion
1186:
1187: This flag is set by T-Kernel/OS.
1188:
1189: (2) Quasi-task portion (extended SVC handler)
1190:
1191: Use a software-like flag in T-Kernel/OS to judge for it.
1192:
1193: 4.3 Exceptions/Interrupts Used by T-Kernel/OS
1194:
1195: Supervisor call (SVC instruction)
1196: - T-Kernel system call or extended SVC SVC 6
1197: - tk_ret_int() system call SVC 7
1198: - Task dispatcher SVC 8
1199: - Debugger support function SVC 9
1200: - Return from task exception SVC 10
1201:
1202: Interrupt
1203: - TI0 timer interrupt IRQ 54
1204:
1205: 4.4 System Call
1206:
1207: The caller invokes the interface library in the form of C language
1208: function call. The interface library is described below.
1209:
1210: The system calls can only be called from the following modes:
1211:
1212: USR: User mode
1213: SYS: System mode
1214: SVC: Supervisor mode
1215:
1216: If you want to call a system call from other modes, you need to switch
1217: the mode to the SVC mode or save R14_svc before calling it (in the
1218: latter case, you need to restore R14_svc back to the original value after
1219: returning from the system call).
1220: Note that you must not switch the mode to the USR or SYS mode.
1221:
1222: If you want to invoke a system call from the assembly language routine,
1223: you should call it via the interface library in the functional form
1224: as in the case of C language programming.
1225: Alternatively, you can call it directly by using an SVC instruction to
1226: perform the processing equivalent to the interface library described
1227: below.
1228: As the register saving rule follows the C language rule, it is also
1229: necessary to save the registers according to the C language rule when
1230: the system call is invoked directly from the assembly language routine.
1231:
1232: (1) T-Kernel/OS system call
1233:
1234: ER tk_xxx_yyy(p1, p2, p3, p4, p5)
1235:
1236: The arguments are integers or pointers, and passed in the same manner as
1237: with the function call in C language.
1238:
1239: // r0 = p1
1240: // r1 = p2
1241: // r2 = p3
1242: // r3 = p4
1243: // +---------------+
1244: // sp ->| p5 |
1245: // | : |
1246: // +---------------+
1247: tk_xxx_yyy:
1248: stmfd sp!, {r4} // Save r4
1249: add r4, sp, #4 // r4 = Parameter's position on the stack
1250: stmfd sp!, {lr} // Save lr
1251: ldr ip, = Function code
1252: svc 6
1253: ldmfd sp!, {lr} // Restore lr
1254: ldmfd sp!, {r4} // Restore r4
1255: bx lr
1256:
1257: (2) Extended SVC
1258:
1259: INT zxxx_yyy( .... )
1260:
1261: Arguments are stored in a pacekt on the caller side, and the address of
1262: the packet is stored in the R0 register before invocation.
1263:
1264: zxxx_yyy:
1265: stmfd sp!, {r0-r3} // Put register arguments on stack and
1266: wrap them into a packet
1267: mov r0, sp // R0 = Address of the argument packet
1268: stmfd sp!, {lr} // Save lr
1269: ldr ip, = Function code
1270: svc 6
1271: ldmfd sp!, {lr} // Restore lr
1272: add sp, sp, #4*4 // Discard arguments on the stack
1273: bx lr
1274:
1275: This method of putting arguments in a packet is just an example.
1276: Arguments must be put in a packet appropriately according the
1277: number of arguments and their types.
1278:
1279: (3) T-Kernel/DS service call
1280:
1281: ER td_xxx_yyy(p1, p2, p3, p4)
1282:
1283: The arguments are four or less integers or pointers, and passed in the
1284: same manner as with the function call in C language.
1285:
1286: // r0 = p1
1287: // r1 = p2
1288: // r2 = p3
1289: // r3 = p4
1290: td_xxx_yyy:
1291: stmfd sp!, {lr} // Save lr
1292: ldr ip, = Function code
1293: svc 9
1294: ldmfd sp!, {lr} // Restore lr
1295: bx lr
1296:
1297: 4.5 Exception/Interrupt Handler
1298:
1299: ER tk_def_int( UINT dintno, T_DINT *pk_dint )
1300:
1301: typedef struct t_dint {
1302: ATR intatr; /* Interrupt handler attribute */
1303: FP inthdr; /* Interrupt handler address */
1304: } T_DINT;
1305:
1306: Specify the index number (0 to 255) of the vector table in dintno.
1307:
1308: FIQ fast interrupt is handled differently from other
1309: exceptions/interrupts. For details, see the explanation of FIQ fast
1310: interrupt later in this document.
1311:
1312: T-Kernel/OS does nothing for handling the interrupt controller. The
1313: interrupt handler is responsible for handling the processing such as
1314: clearing interrupts.
1315:
1316: To enable multiple interrupts, you need to manipulate the interrupt mask
1317: register of the interrupt controller (or the GPIO controller) to set the
1318: controller to disable interrupts other than those allowed for multiple
1319: interrupts. Especially, be careful not to cause the same interrupt to
1320: reenter.
1321: If you modify the interrupt mask of the interrupt controller
1322: (or the GPIO controller), you need restore it before returning from the
1323: interrupt handler.
1324:
1325: The exception/interrupt handler enters one of the following processor
1326: modes depending on the type of the exception/interrupt that occurred.
1327:
1328: SVC: Supervisor mode
1329: ABT: Abort mode
1330: UND: Undefined instruction exception mode
1331: IRQ: Interrupt mode
1332: FIQ: Fast interrupt mode
1333:
1334: However, when TA_HLNG is specified for a handler, the mode is automatically
1335: changed to the SVC mode by a high-level language support routine. Therefore,
1336: regardless of which type of exception/interrupt occurred, the mode upon
1337: entry into the user's interrupt handler is always the SVC mode.
1338:
1339: (1) In the case of TA_HLNG being specified for the exception/interrupt handler
1340:
1341: The format of an exception/interrupt handler is as follows.
1342:
1343: void inthdr( UINT dintno, void *sp )
1344:
1345: dintno The index number of the vector table of the
1346: exception/interrupt that occurred
1347: For the default handler, it is the index number of the
1348: exception/interrupt that occurred, not the index number
1349: of the default handler.
1350:
1351: sp The pointer to the following information saved on the stack
1352:
1353: +---------------+
1354: sp -> | R12=ip |
1355: | R14=lr | <- Return address
1356: | SPSR |
1357: +---------------+
1358:
1359: Return address
1360: IRQ Return address from interrupt
1361: SVC address of the next instruction that follows SVC instruction
1362: ABT address if the aborted instruction
1363: UND address of the next instruction that follows the undefined
1364: instruction
1365:
1366: - The state of CPU upon entry into the exception/interrupt handler is as follows:
1367:
1368: CPSR.F = ? Remains as is when interrupt/exception occurs
1369: CPSR.I = 1 Interrupt disabled
1370: CPSR.A = 1 Abort exception disabled
1371: CPSR.M = 19 SVC: Supervisor mode
1372:
1373: Multiple interrupts are disabled. Setting CPSR.I to 0 can enable
1374: multiple interrupts. In that case, the interrupt controller setting
1375: should be modified appropriately.
1376:
1377: - You return from the exception/interrupt handler by returnin from the function.
1378:
1379: - The address of the high-level language support routine in T-Kernel/OS is
1380: stored in the vector table, and the specified handler is called from the
1381: high-level language support routine.
1382:
1383: (2) In the case of TA_ASM being specified for the exception/interrupt handler
1384:
1385: - The address of the specified exception/interrupt handler is directly
1386: stored in the vector table. Therefore, the handler is directly called
1387: without going through T-Kernel/OS.
1388:
1389: - Not going through T-Kernel/OS means that the flag for determining the
1390: task-independent portion is not updated. As the task-independent portion
1391: is not identified as such, the following points need to be noted.
1392:
1393: - If interrupts are enabled (CPSR.I = 0, and A = 0), there is a
1394: possibility that task dispatching will occur. If task dispatching
1395: occurs, the subsequent operations will be abnormal except when a
1396: supervisor call exception caused by a SVC instruction occurs.
1397: - When a system call is invoked, it will be processed as having been
1398: called from a task portion.
1399:
1400: Therefore, if it is necessary to issue a system call in a handler, or if
1401: you want to enable interrupts, the flag for determining the
1402: task-independent portion must be set as necessary.
1403: It is also desirable to switch to the SVC mode in advance to issue a
1404: system call. (See the above explanation of system call)
1405:
1406: The flag for determining the task-independent portion can be set by
1407: manipulating the `taskindp' flag in the system shared information. Note
1408: that it must be performed in the interrupt disabled state
1409: (CPSR.I = 1 and A = 1). It is also necessary to restore the flag before
1410: exiting the interrupt handler.
1411:
1412: taskindp++; /* Enter the task-independent portion */
1413:
1414: taskindp--; /* Leave the task-independent portion */
1415:
1416: As multiple interrupts may occur, taskindp must be set by
1417: increment/decrement. Do not use, for example, taskindp = 0.
1418:
1419: - To return from the exception/interrupt handler, use the tk_ret_int()
1420: system call or the EIT_RETURN macro (or the INT_RETURN or EXC_RETURN
1421: macro depending on the processor mode). If you use the macro,
1422: the delayed dispatch does not occur.
1423: It is also possible to perform equivalent processing instead of
1424: using the macro directly.
1425:
1426: - Unlike other system calls, the tk_ret_int() system call is called
1427: by a separate dedicated trap. It cannot be called in the same function
1428: form like other system calls.
1429:
1430: SVC 7 // tk_ret_int() call (not return)
1431:
1432: Prior to calling tk_ret_int(), the stack must be configured
1433: in the following state.
1434: It is also necessary to restore all registers except those
1435: (R0 to R11) stored on the stack.
1436: The exception mode must be restored to the mode of the
1437: exception/interrupt that occurred (then current mode upon entry into
1438: the handler). sp is the stack pointer (R13) for processing in the
1439: mode of the exception/interrupt that occurred.
1440:
1441: +---------------+
1442: sp -> | R14_svc |
1443: | R12=ip |
1444: | R14=lr | <- Return address
1445: | SPSR |
1446: +---------------+
1447:
1448: In the above stack, R14_svc stores the value of the R14 register of the
1449: SVC mode upon entry into the handler. Other values are saved by the
1450: exception branch processing routine of T-Monitor.
1451:
1452: If tk_ret_int() is called from other than an exception/interrupt
1453: handler, the behavior is not guaranteed.
1454:
1455: The macros ENTER_SVC_MODE for switching the mode to the SVC mode and
1456: TK_RET_INT for calling tk_ret_int() are provided.
1457:
1458: (3) FIQ Fast interrupt
1459:
1460: The FIQ fast interrupt handler is executed outside the OS control.
1461: FIQ is used for fast data transfer or other applications that does not
1462: require the support of OS.
1463:
1464: - The TA_HLNG attribute cannot be specified for the FIQ fast interrupt
1465: handler.
1466: - The FIQ fast interrupt handler cannot be exited by calling the
1467: tk_ret_int() system call.
1468: - None of system calls and extended SVCs can be called in the FIQ fast
1469: interrupt handler.
1470: - IRQ normal interrupts or abort exceptions must not be enabled in the
1471: FIQ fast interrupt handler.
1472:
1473: If you want to disable FIQ fast interrupts by using the CPSR.F flag
1474: outside the FIQ fast interrupt handler itself, IRQ interrupts and abort
1475: exceptions must also be disabled.
1476: That is, you need to set CPSR.F=1, CPSR.I=1, and CPSR.A=1, and must not
1477: enable either or both of IRQ and abort exception while FIQ is disabled.
1478: In addition, none of system calls and extended SVCs can be called while
1479: the FIQ interrupt is disabled.
1480:
1481: Disabling FIQ is avoided in OS so that FIQ has faster interrupt
1482: response than IRQ. These restrictions are the trade-off of such fast
1483: interrupt response. If they are not properly adhered to, OS may
1484: malfunction.
1485:
1486:
1487: 4.6 Task
1488:
1489: ER tk_cre_tsk( T_CTSK *ctsk )
1490:
1491: typedef struct t_ctsk {
1492: void *exinf; /* Extended information */
1493: ATR tskatr; /* Task attribute */
1494: FP task; /* Task start address */
1495: PRI itskpri; /* Initial task priority */
1496: INT stksz; /* User stack size (in bytes) */
1497: INT sstksz; /* System stack size (in bytes) */
1498: void *stkptr; /* User stack pointer */
1499: void *uatb; /* Task space page table */
1500: INT lsid; /* Logical space ID */
1501: ID resid; /* Resource ID */
1502: } T_CTSK;
1503:
1504: (1) Option specification
1505:
1506: tskatr := (TA_ASM || TA_HLNG)
1507: | [TA_SSTKSZ] | [TA_USERSTACK] | [TA_TASKSPACE] | [TA_RESID]
1508: | (TA_RNG0 || TA_RNG1 || TA_RNG2 || TA_RNG3)
1509: | [TA_FPU]
1510:
1511: - TA_COPn is not used. As FPU(VFP) is not supported, TA_FPU = 0 holds.
1512:
1513: - lsid is set into the context ID register (CONTEXTIDR(CP15.c13.0.c0.1)).
1514: The valid range for lsid is 0 to 255.
1515: uatb is set into the translation table base register 0
1516: (TTBR0(CP15.c2.0.c0.0)).
1517:
1518: (2) Task form
1519:
1520: The task takes the following form for either TA_HLNG or TA_ASM option:
1521:
1522: void task( INT stacd, void *exinf )
1523:
1524: The state of registers when the task is started are as follows:
1525:
1526: CPSR.F = 0 Fast interrupt enabled
1527: CPSR.I = 0 Interrupt enabled
1528: CPSR.A = 0 Abort exception enabled
1529: CPSR.T,J = 0,0 ARM mode When the least significant bit
1530: of the task start address is 0
1531: 1,0 Thumb mode When the least significant bit
1532: of the task start address is 1
1533: CPSR.M = 16 USR: User mode When TA_RNG3 is specified
1534: 31 SYS: System mode When TA_RNG1 to 2 is specified
1535: 19 SVC: Supervisor mode When TA_RNG0 is specified
1536:
1537: R0 = stacd Task start parameter
1538: R1 = exinf Task extended information
1539: R13(sp) Stack pointer
1540:
1541: Other registers are undefined.
1542:
1543: To exit a task, it is necessary to use tk_ext_tsk() or tk_exd_tsk().
1544: A simple return does not exit the task. The correct behavior is
1545: not guaranteed after the return.
1546:
1547: 4.7 Set/Get Task Registers
1548:
1549: ER tk_set_reg( ID tskid, T_REGS *regs, T_EIT *eit, T_CREGS *cregs )
1550: ER tk_get_reg( ID tskid, T_REGS *regs, T_EIT *eit, T_CREGS *cregs )
1551:
1552: typedef struct t_regs {
1553: VW r[13]; /* General registers R0 to R12 */
1554: void *lr; /* Link register R14 */
1555: } T_REGS;
1556:
1557: typedef struct t_eit {
1558: void *pc; /* Program counter R15 */
1559: UW cpsr; /* Program status register */
1560: UW taskmode; /* Task mode flag */
1561: } T_EIT;
1562:
1563: typedef struct t_cregs {
1564: void *ssp; /* System stack pointer R13_svc */
1565: void *usp; /* User stack pointer R13_usr */
1566: void *uatb; /* Task space page table address
1567: */
1568: UW lsid; /* Task logical space ID */
1569: } T_CREGS;
1570:
1571: - cpsr cannot be changed except in the flag fields
1572: (excluding J and IT bits) (bit 31 to 27). Settings in other fields
1573: (bit 26 to 0) are ignored.
1574:
1575: - taskmode is same as the task mode flag stored in the system shared
1576: information. It is treated as the register for holding the information
1577: about memory access privilege.
1578:
1579: - If you set the registers of the task in DORMANT state, the task start
1580: parameter and task extended information are set to R0 and R1 by
1581: tk_sta_tsk(), so the values set by tk_set_reg() will be discarded.
1582:
1583: 4.8 Task Exception Handler
1584:
1585: A task exception handler should have the dedicated entry routine for
1586: saving/restoring the registers. For the entry routine, use the macro
1587: TEXHDR_ENTRY.
1588: You can perform an equivalent processing instead of using the macro
1589: directly.
1590:
1591: State of the stack upon entry into the task exception handler
1592:
1593: +---------------+
1594: sp -> |texcd | Exception code
1595: |PC | Return address from handler
1596: |CPSR | CPSR to be restored at return from handler
1597: +---------------+
1598:
1599: 4.9 System Call/Extended SVC Caller Information
1600:
1601: The system call/extended SVC caller information passed to the hook
1602: routine defined by td_hok_svc() is in the following form:
1603:
1604: typedef struct td_calinf {
1605: void *ssp; /* System stack pointer */
1606: void *r11; /* Frame pointer upon entry */
1607: } TD_CALINF;
1608:
1609: ssp shows the position of the stack just after the exception branch
1610: routine of T-Monitor is completed, and the content of the stack is as
1611: follows:
1612:
1613: +---------------+
1614: ssp -> |R12=ip |
1615: |R14_svc=lr | Return address from SVC
1616: |SPSR | Processor mode of the caller
1617: +---------------+
1618: +---------------+
1619: R13_xxx -> |R14_xxx=lr | Return address from the interface library
1620: +---------------+
1621:
1622: The return address from the system call/extended SVC is R14_svc.
1623: However, they are usually called by using the interface library, so
1624: R14_svc points the address of the interface library.
1625:
1626: The return address from the interface library is R14_xxx. R13_xxx is a
1627: stack pointer based on the processor mode of the caller, and the
1628: processor mode of the caller can be found from SPSR. If the processor
1629: mode of the original caller is SVC, ssp + 12 is equivalent to R13_xxx.
1630: If you do not use the standard interface library, this may not be
1631: the case.
1632:
1633: 4.10 CPU Interrupt Control
1634:
1635: The CPU interrupt control macro functions shown below disable/enable the
1636: CPSR.I and A flags.
1637: They do not change the CPSR.F flag. That means they control the IRQ, i.e.,
1638: normal interrupts, and abort exception interrupts, and they do not affect
1639: the FIQ, i.e. fast interrupts.
1640:
1641: DI( UINT intsts ) IRQ interrupt disabled
1642: EI( UINT intsts ) IRQ interrupt enabled (restored to the previous state)
1643:
1644: 4.11 Interrupt controller
1645:
1646: The following library functions are provided to operate the interrupt
1647: controllers:
1648:
1649: (1) Value of interrupt vector (INTVEC)
1650:
1651: #define IV_IRQ(n) ( 32 + (n) ) /* IRQ interrupt 0 to 95 */
1652: #define IV_GPIO(n) ( 128 + (n) ) /* GPIO interrupt 0 to 127 */
1653:
1654: The value that can be specified as intvec in the interrupt controller
1655: operation function is in the valid range of IRQ and GPIO interrupts.
1656: If you specify an invalid value (outside the valid range),
1657: the subsequent correct behavior is not guaranteed.
1658:
1659: (2) Set interrupt mode
1660:
1661: void SetIntMode( INTVEC intvec, UINT mode )
1662:
1663: Sets the interrupt specified by `intvec' for the mode specified by `mode'.
1664: If an invalid mode is specified, the subsequent correct
1665: behavior is not guaranteed.
1666:
1667: #define IM_ENA 0x0001 /* Interrupt line enabled */
1668: #define IM_DIS 0x0000 /* Interrupt line disabled */
1669: #define IM_INV 0x0002 /* Inverted polarity */
1670: #define IM_LEVEL 0x0200 /* Level */
1671: #define IM_EDGE 0x0000 /* Edge */
1672: #define IM_HI 0x0000 /* High level/rising edge */
1673: #define IM_LOW 0x0100 /* Low level/falling edge */
1674: #define IM_BOTH 0x0400 /* Both edges */
1675: #define IM_ASYN 0x0800 /* Asynchronous */
1676:
1677: For IRQ
1678: mode := IM_ENA | IM_INV
1679: or IM_DIS
1680:
1681: For GPIO
1682: mode := IM_ENA | IM_LEVEL | (IM_HI || IM_LOW) | IM_ASYN
1683: or IM_ENA | IM_EDGE | (IM_HI || IM_LOW || IM_BOTH) | IM_ASYN
1684: or IM_DIS
1685:
1686: If IM_ENA is specified, the specified mode is set, interrupts are
1687: disabled (DisableInt), and then the interrupt line is enabled.
1688: If IM_DIS is specified, the interrupt line is disabled. For the disabled
1689: interrupt line, no interrupt occurs even when interrupts are enabled
1690: (EnableInt).
1691: In the initial state, the interrupt lines are disabled (IM_DIS).
1692:
1693: When the system is started, the setting of the interrupt
1694: controller for the following GPIO interrupts is IM_ENA, which
1695: means that the following interrupts are enabled (EnableInt).
1696:
1697: IRQ26 GIO6 Interrupt (GPIO port 96 to 111)
1698: IRQ27 GIO7 Interrupt (GPIO port 112 to 127)
1699: IRQ50 GIO0 Interrupt (GPIO port 0 to 15)
1700: IRQ51 GIO1 Interrupt (GPIO port 16 to 31)
1701: IRQ52 GIO2 Interrupt (GPIO port 32 to 47)
1702: IRQ53 GIO3 Interrupt (GPIO port 48 to 63)
1703: IRQ79 GIO4 Interrupt (GPIO port 64 to 79)
1704: IRQ80 GIO5 Interrupt (GPIO port 80 to 95)
1705:
1706: (3) Enable interrupt
1707:
1708: void EnableInt( INTVEC intvec )
1709:
1710: Enables the interrupt specified by intvec.
1711:
1712: (4) Disable interrupt
1713:
1714: void DisableInt( INTVEC intvec )
1715:
1716: Disables the interrupt specified by intvec.
1717:
1718: (5) Clear interrupt request
1719:
1720: void ClearInt( INTVEC intvec )
1721:
1722: Clears the interrupt request specified by intvec.
1723:
1724: Only an edge-triggered interrupt needs be cleared.
1725:
1726: (6) Check for interrupt request
1727:
1728: BOOL CheckInt( INTVEC intvec )
1729:
1730: Check whether or not there is the interrupt request specified by intvec.
1731: If there is an interrupt request, TRUE (other than 0) is returned.
1732:
1733: The raw status register is probed to check for an interrupt request.
1734:
1735: 4.12 I/O Port Access to Peripheral Device areas
1736:
1737: The memory type mode setting for peripheral device areas is "Device".
1738: Hence, if we use out_b(), out_h(), out_w(), and out_d() to these areas,
1739: the call returns before the completion of drain (i.e., the writing of data).
1740: (See 2.3 Memory Map for peripheral device areas.)
1741:
1742: 5. Device Driver Implementation Specification
1743:
1744: 5.1 System Disk Driver
1745:
1746: (1) Supported devices
1747:
1748: This driver supports the following system disks:
1749:
1750: - microSD card inserted into the microSD card slot
1751: - ROM disk (NOR Flash)
1752:
1753: Device name Device
1754: pcb microSD card
1755: rda ROM disk (NOR Flash)
1756:
1757: Only the following device supports subunits.
1758:
1759: microSD card
1760: * Up to four subunits
1761:
1762: Accessing the microSD card uses the following resource of EM1-D512:
1763:
1764: Media Controller GPIO for card detection
1765: microSD SDIA(SD0) GPIO P3
1766:
1767: The interrupts of SDIA (SDIx_SD_INT, SDIx_CC_INT) are not used.
1768: It is assumed that the I/O pin setting and the clock setting that are
1769: necessary to use SDIA and GPIO have been performed appropriately.
1770:
1771: The ROM disk using FlashROM (NOR) uses the area defined in RomInfo as
1772: disk.
1773:
1774: (2) Hardware-dependent items (system disk driver)
1775:
1776: (a) DEVCONF entries
1777:
1778: The system disk driver refers to the following DEVCONF entries:
1779:
1780: HdSpec HD specification
1781: xxNI xxxx xxxx xxxx xxxx
1782: [Default: 0x00010000]
1783:
1784: I : Automatically check for insertion of the ejectable disk media
1785: N : Disable automatic ejection of the ejectable disk media
1786:
1787: HdChkPeriod interval (msec)
1788: Ejectable disk check interval
1789: [Default: 3000]
1790:
1791: (b) Master boot record access function
1792:
1793: A special function is provided for accessing the master boot record of a
1794: device that supports subunits (the physical unit only).
1795:
1796: Attribute record number: -999999 (R)
1797:
1798: data: UW magic;
1799: DiskBlock0 mboot;
1800:
1801: magic = CH4toW('M','B','R','R') : Read from master boot record
1802: CH4toW('M','B','R','W') : Write to master boot record
1803: (write in read processing)
1804:
1805: * CH4toW(c1, c2, c3, c4) is ( ((c4)<<24)|((c3)<<16)|((c2)<<8)|(c1) ).
1806:
1807: * The subsequent correct behavior is not guaranteed if a partition
1808: in use is changed by writing to the master boot record.
1809:
1810: (c) Partition (subunit) handling
1811:
1812: For a device that supports subunits, always four partitions (subunits)
1813: are registered in order to respond to dynamic changes of the partition
1814: information. An attempt to open an empty partition results in the
1815: E_NOMDA error.
1816:
1817: (d) How to calculate CHS information
1818:
1819: Generally, the total disk capacity that is calculated from the CHS is
1820: less than the actual total disk capacity.
1821:
1822: Cylinders (C) Max. 1023
1823: Heads (H) Max. 255
1824: Sectors (S) Max. 63
1825:
1826: - The maximum value of C is 1024, but normally the last cylinder is not
1827: used.
1828: - The maximum number of H is 256, but the usual number is 255.
1829:
1830: The CHS information is determined as follows:
1831:
1832: 1. From the physical CHS information, the acceptable used
1833: CHS information is calculated
1834: so as to keep the above limitations as follows
1835: (pC, pH, pS : physical CHS information).
1836: T = pC * pH * pS; C = pC; H = pH; S = pS;
1837: while (C > 1024) {C >>= 1; H <<= 1;}
1838: if (S > 63) S = 63;
1839: if (H > 255) H = 255;
1840: C = T / H / S;
1841: if (C > 1023) C = 1023;
1842:
1843: 2. When a partition is already set, the CHS information is calculated
1844: from the partition information.
1845: S = Last sector of partition;
1846: H = Last head of partition + 1;
1847: C = T / H / S - 1;
1848:
1849: 5.2 Clock Driver
1850:
1851: (1) Supported devices
1852:
1853: This driver supports SPI (SP0) of EM1-D512 and RTC (RX-4581NB)
1854: connected to it.
1855: Besides RTC, an Audio CODEC (ML7037) and a power supply management
1856: controller (DA9052) are connected to SP0, so this driver also offers the
1857: interface for operating SPI.
1858:
1859: The device name is "CLOCK".
1860:
1861: (2) Hardware limitations (clock driver)
1862:
1863: Non-volatile register (free register) is not supported.
1864: RTC interrupt is not supported.
1865:
1866: (a) DN_CKAUTOPWON: Set/get the automatic power-on time (RW)
1867:
1868: Not supported. An error (E_NOSPT) will be returned.
1869:
1870: (b) DN_CKREGISTER: Read/write a non-volatile register (RW)
1871:
1872: Not supported. An error (E_NOSPT) will be returned.
1873:
1874: As DN_CKAUTOPWON is not supported, events notification do not take place.
1875:
1876: (3) Interface for operating SPI(SP0)
1877:
1878: The RTC, the Audio CODEC, and the power supply management controller
1879: that are connected to SPI (SP0) are operated by using the following
1880: interface:
1881:
1882: <device/em1d512/em1d512_iic.h>
1883: ER em1d512_spixfer(W cs, UB *xmit, UB *recv, W len)
1884:
1885: This interface sends/receives data to/from the devices connected to
1886: SPI(SP0).
1887:
1888: cs: target device for communiation
1889: 0 Power supply management controller (DA9052)
1890: 1 Audio CODEC (ML7037)
1891: 2 RTC (RX-4581NB)
1892:
1893: xmit: address of the area that holds the sent data
1894: recv: address of the area to store the received data
1895: len: Number of sent/received data (byte)
1896:
1897: Return code: E_OK or an error (E_IO, E_TMOUT, E_PAR)
1898:
1899: This interface operates by using the SP0 interrupt, so it must not be
1900: called in an interrupt handler or while interrupts are disabled. To wait
1901: for an SP0 interrupt, use tk_slp_tsk ().
1902:
1903: 5.3 Screen (Display Driver)
1904:
1905: (1) Supported devices
1906:
1907: This driver uses the LCD controller installed in EM1-D512. It uses the
1908: MEMC-LCD DirectPath mode to operate the device without IMC
1909:
1910: (image composer).
1911: Besides the LCD controller, GPIO P82 and the White LED Driver of DA9052
1912: are used to control the LCD lighting.
1913: It is assumed that the I/O pin setting that is necessary to use LCD
1914: has been performed appropriately. The pixel clock used for display
1915: is generated by the screen driver by manipulating PLL2.
1916:
1917: (2) Hardware-dependent items (screen driver)
1918:
1919: The attribute data that can be used by the screen driver has restrictions.
1920:
1921: (a) DN_SCRNO: Get/set the display mode to be used (RW)
1922:
1923: Only getting the display mode (R) is supported.
1924:
1925: (b) DN_SCRUPDFN: Get the screen update function (R)
1926:
1927: Not supported.
1928: The function pointer is set to NULL.
1929:
1930: (c) DN_SCRVFREQ: Set/get the vertical frequency of monitor (RW)
1931:
1932: Not supported.
1933: Get: vfreq is set to 0.
1934: Set: the value of vfreq is ignored.
1935:
1936: (d) DN_SCRBRIGHT: Set/get the screen brightness (RW)
1937:
1938: (e) DN_SCRUPDRECT: Update the screen display (W)
1939:
1940: (f) DN_SCRADJUST: Set/get the monitor timing adjustment (RW)
1941:
1942: (g) DN_SCRMEMCLK: Set/get the clock of Video-RAM (RW)
1943:
1944: (h) DN_SCRWRITE: Direct screen display (W)
1945:
1946: Not supported. An error (E_NOSPT) is returned.
1947:
1948: (i) Supported display mode
1949:
1950: Only the following display mode is supported.
1951:
1952: 800 x 480, 16 bpp fixed
1953:
1954: (j) Set the display mode
1955:
1956: As the display mode is only set at system startup, the function of
1957: dynamically setting it as attribute data is not supported.
1958:
1959: (k) Set the vertical frequency (refresh rate)
1960:
1961: The vertical frequency setting function is not supported.
1962:
1963: (l) DEVCONF entries
1964:
1965: The screen driver refers to the following DEVCONF entries:
1966:
1967: VIDEOMODE mode
1968:
1969: This entry is reserved (must not be used).
1970:
1971: VIDEOATTR attr
1972:
1973: This entry is reserved (must not be used).
1974:
1975: 5.4 KB/PD Driver
1976:
1977: (1) Supported devices
1978:
1979: - Keypad
1980: - Touch panel
1981:
1982: The keypad uses GPIO P4(SW4), P6(SW3), and P7(SW2). The key ON/OFF is
1983: detected by using these GPIO interrupts.
1984: The A/D conversion value of the touch panel is obtained from the power
1985: supply management controller (DA9052) by using the interface for
1986: operating SPI (SP0) which is provided by the RTC driver. The
1987: following values are set to the interrupt mask register of DA9052
1988: to allow only PEN_DOWN interrupts to occur. Interrupts from DA9052
1989: are raised as GPIO P0 interrupt.
1990:
1991: R10(IRQ_MASK_A) 0xff
1992: R11(IRQ_MASK_B) 0xbf
1993: R12(IRQ_MASK_C) 0xff
1994: R13(IRQ_MASK_D) 0xff
1995:
1996: (2) Hardware-dependent items (KB/PD driver)
1997:
1998: (a) DEVCONF entries
1999:
2000: The real I/O driver (lowkbpd) refers to the following DEVCONF entries.
2001:
2002: TEngTabletPar X-bias X-span Y-bias Y-span PointerNoDisp ScanRate(off)
2003: ScanRate(on)
2004: X-bias, X-span, Y-bias, and Y-span are the corrective parameters
2005: which are used to normalize the coordinate data obtained from
2006: the touch pad.
2007: If PointerNoDisp is specified to 1, the pointer is not displayed
2008: (MetaBut.nodsp = 1 is passed).
2009: For ScanRate(off), specify the time, in milliseconds, until the
2010: next pen touch detection is performed after the pen is released.
2011: For ScanRate(on), specify the polling interval during pen touch
2012: in milliseconds.
2013:
2014: The default values; PointerNoDisp = 0, ScanRate(off) = 50,
2015: ScanRate(on) = 50, and the values of X-bias, X-span, Y-bias, and
2016: Y-span vary depending on the used LCD panel.
2017:
2018: TEngUseTablet Whether the touch panel can be used or not
2019: If 1 is specified, the touch panel is used.
2020: If 0 is specified, the touch panel is not used.
2021:
2022: The default is 1.
2023:
2024: (b) Notes on push button switches
2025:
2026: The following shows the correspondence between the push button switches
2027: and the scan codes:
2028:
2029: SW2 SW3 SW4
2030: ------------------------
2031: 0x6e 0x6d 0x6f
2032:
2033: 5.5 RS-232C Driver
2034:
2035: (1) Supported devices
2036:
2037: This driver supports UART0, UART1, and UART2 built in EM1-D512.
2038: It is assumed that the I/O pin setting and the clock setting that are
2039: necessary to use these UARTs have been performed appropriately.
2040:
2041: The RS-232C device names, the corresponding ports, and the used
2042: resources are shown below.
2043:
2044: Port name Address Interrupt
2045: "rsa" (UART0) 0x50000000 to 0x5000ffff IV_IRQ(9)
2046: "rsb" (UART1) 0x50010000 to 0x5001ffff IV_IRQ(10)
2047: "rsc" (UART2) 0x50020000 to 0x5002ffff IV_IRQ(11)
2048:
2049: As the following signal lines are not output from the chip, the
2050: functions related to these signal lines cannot (must not) be used.
2051:
2052: UART0 RI, DSR, DTR, RTS, CTS
2053: UART1 RI, DSR, DTR, RTS, CTS
2054: UART2 RI, DSR, DTR
2055:
2056: (2) Hardware-dependent items (RS driver)
2057:
2058: (a) Attribute data
2059:
2060: The attribute data that can be set by the RS driver, and the range of
2061: parameters that can be set to the attribute data are shown below.
2062:
2063: (b) DN_RSMODE: Communication mode (RW)
2064:
2065: The following mode is supported.
2066:
2067: parity: 0: none, 1: odd, 2: even
2068: datalen: 0:5 bits, 1:6 bits, 2:7 bits, 3:8 bits
2069: stopbits: 0:1 bit, 1:1.5 bits, 2:2 bits
2070: baud: 300 to 115200
2071:
2072: (c) DN_RSFLOW: Flow control (RW)
2073:
2074: For UART0 and UART1, csflow and rsflow must be set to 0.
2075:
2076: (d) DN_RSSTAT: Line status (R)
2077:
2078: As some of signal lines are not available, the following values have no
2079: meaning:
2080:
2081: UART0 CI(RI), CD(DCD), DR(DSR), CS(CTS)
2082: UART1 CI(RI), CD(DCD), DR(DSR), CS(CTS)
2083: UART2 CI(RI), CD(DCD), DR(DSR)
2084:
2085: (3) Hardware-dependent items (Serial I/O driver)
2086:
2087: (a) Correspondence between port numbers and devices
2088:
2089: The following shows the correspondence of the port numbers
2090: specified in serial_in(), serial_out(), and serial_ctl() of the serial
2091: I/O driver and the devices denoted by the numbers.:
2092:
2093: port Device
2094: 0 UART0
2095: 1 UART1
2096: 2 UART2
2097: 3 Reserved
2098:
2099: (b) Limitations on serial_ctl()
2100:
2101: There are restrictions on the specifications of kind and arg of
2102: ER serial_ctl (W port, W kind, UW *arg).
2103:
2104: <kind> <arg>
2105: DN_RSFLOW RsFlow Flow control
2106:
2107: - See the section about DN_RSFLOW of the RS driver about
2108: setting RsFlow.
2109:
2110: - DN_RSSTAT RsStat Get line status
2111:
2112: - See the section about DN_RSSTAT of the RS driver about
2113: the obtained RsStat value.
2114:
2115: RS_LINECTL UW Set control line ON/OFF
2116:
2117: - Attempts to operate the signal lines by specifying the
2118: followings make no sense.
2119: UART0 RSCTL_DTR, RSCTL_RTS
2120: UART1 RSCTL_DTR, RSCTL_RTS
2121: UART2 RSCTL_DTR
2122:
2123: END.