| tkernel_2/driver/tef_em1d/console/src/ns16450.h | bare source | permlink (0.04 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * T-Kernel 2.0 Software Package 4: * 5: * Copyright 2011 by Ken Sakamura. 6: * This software is distributed under the latest version of T-License 2.x. 7: *---------------------------------------------------------------------- 8: * 9: * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17. 10: * Modified by T-Engine Forum at 2013/03/01. 11: * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01. 12: * 13: *---------------------------------------------------------------------- 14: */ 15: 16: /* 17: * ns16450.h Console/Low-level serial I/O driver 18: * 19: * General definition of serial controller (NS16450, NS16550) 20: */ 21: 22: /* Individual definition is required for "_IOADR(n)" and "_CLOCK (Hz)" */ 23: 24: /* I/O port address */ 25: #if _TEF_EM1D_ 26: #define SC_DATA _IOADR(0) /* Data register R/W */ 27: #define SC_INTE _IOADR(1) /* Interrupt-enabled register R/W */ 28: #define SC_INTS _IOADR(2) /* Interrupt ident register R */ 29: #define SC_FCTL _IOADR(3) /* FIFO control register W */ 30: #define SC_LCTL _IOADR(4) /* Line control register R/W */ 31: #define SC_MCTL _IOADR(5) /* Modem control register R/W */ 32: #define SC_LSTS _IOADR(6) /* Line status register R */ 33: #define SC_MSTS _IOADR(7) /* Modem status register R */ 34: #define SC_SCRA _IOADR(8) /* Temporary data register R/W */ 35: #define SC_DIVL _IOADR(9) /* Freq dividing count lower R/W */ 36: #define SC_DIVH _IOADR(10) /* Freq dividing count upper R/W */ 37: #else 38: #define SC_DATA _IOADR(0) /* Data register R/W */ 39: #define SC_INTE _IOADR(1) /* Interrupt-enabled register R/W */ 40: #define SC_INTS _IOADR(2) /* Interrupt ident register R */ 41: #define SC_FCTL _IOADR(2) /* FIFO control register W */ 42: #define SC_LCTL _IOADR(3) /* Line control register R/W */ 43: #define SC_MCTL _IOADR(4) /* Modem control register R/W */ 44: #define SC_LSTS _IOADR(5) /* Line status register R */ 45: #define SC_MSTS _IOADR(6) /* Modem status register R */ 46: #define SC_SCRA _IOADR(7) /* Temporary data register R/W */ 47: #define SC_DIVL _IOADR(0) /* Freq dividing count lower R/W */ 48: #define SC_DIVH _IOADR(1) /* Freq dividing count upper R/W */ 49: #endif 50: 51: /* Communication speed -> frequency dividing count value */ 52: #define SC_LINE_SPEED(bps) ( _CLOCK / 16 / (bps) ) 53: 54: /* Line control register */ 55: #define LC_DLAB 0x80 /* Frequency dividing counter access */ 56: #define LC_SBRK 0x40 /* Break sending */ 57: #define LC_STKP 0x20 /* Parity fix */ 58: #define LC_EVNP 0x10 /* Even parity */ 59: #define LC_ENAP 0x08 /* Enable parity */ 60: #define LC_STOP 0x04 /* Stop bit */ 61: #define LC_BLEN 0x03 /* The number of data bits */ 62: 63: #define LC_NoParity (0x00) 64: #define LC_EvenParity (LC_ENAP|LC_EVNP) 65: #define LC_OddParity (LC_ENAP) 66: 67: /* Line status register */ 68: #define LS_RFER 0x80 /* Error in the receive FIFO */ 69: #define LS_TSRE 0x40 /* Send shift register is empty */ 70: #define LS_THRE 0x20 /* Send hold register is empty*/ 71: #define LS_BINT 0x10 /* Receive break */ 72: #define LS_FERR 0x08 /* Framing error */ 73: #define LS_PERR 0x04 /* Parity error */ 74: #define LS_OERR 0x02 /* Overrun error */ 75: #define LS_DRDY 0x01 /* There is the receive data */ 76: /* Additional definition for driver internal processing */ 77: #define LS_RXOV 0x80 /* Receive-buffer overflow */ 78: 79: #define LS_RxERR (LS_BINT|LS_FERR|LS_PERR|LS_OERR) 80: 81: /* Modem control register */ 82: #define MC_LOOP 0x10 /* Loopback test mode */ 83: #define MC_OUT2 0x08 /* User-specified aux output #2 */ 84: #define MC_OUT1 0x04 /* User-specified aux output #1 */ 85: #define MC_RTS 0x02 /* Request To Send */ 86: #define MC_DTR 0x01 /* Data Terminal Ready */ 87: 88: /* Modem status register*/ 89: #define MS_CD 0x80 /* Data Carrier Detect */ 90: #define MS_RI 0x40 /* Ring Indicate */ 91: #define MS_DR 0x20 /* Data Set Ready */ 92: #define MS_CS 0x10 /* Clear To Send */ 93: #define MS_D_CD 0x08 /* Change of CD */ 94: #define MS_D_RI 0x04 /* Change of RI */ 95: #define MS_D_DR 0x02 /* Change of DR */ 96: #define MS_D_CS 0x01 /* Change of CS */ 97: 98: /* Interrupt-enabled register */ 99: #define IM_MSTS 0x08 /* Modem status interrupt */ 100: #define IM_LSTS 0x04 /* Receive line status interrupt */ 101: #define IM_SND 0x02 /* Send-enabled interrupt */ 102: #define IM_RCV 0x01 /* Receive-data-enabled interrupt */ 103: 104: #define IM_NORM (IM_LSTS|IM_SND|IM_RCV|IM_MSTS) 105: 106: /* Interrupt identification register */ 107: #define IS_PEND 0x01 /* Interrupt pending */ 108: #define IS_ID 0x0e /* Interrupt ID */ 109: #define IS_CTMO 0x0c /* ID=6 char time-out interrupt */ 110: #define IS_LSTS 0x06 /* ID=3 rcv-line status interrupt */ 111: #define IS_RCV 0x04 /* ID=2 rcv-data-enabled interrupt */ 112: #define IS_SND 0x02 /* ID=1 send-enabled interrupt */ 113: #define IS_MSTS 0x00 /* ID=0 modem status interrupt */ 114: #define IS_FIFO 0xc0 /* FIFO during use */ 115: 116: /* FIFO control register */ 117: #define FC_TL01 0x00 /* Receive-interrupt unit 1 byte */ 118: #define FC_TL04 0x40 /* Receive-interrupt unit 4 byte */ 119: #define FC_TL08 0x80 /* Receive-interrupt unit 8 byte */ 120: #define FC_TL14 0xc0 /* Receive-interrupt unit 14 byte */ 121: #define FC_TXCLR 0x04 /* Send FIFO clear */ 122: #define FC_RXCLR 0x02 /* Receive FIFO clear*/ 123: 124: #if _TEF_EM1D_ 125: #define FC_FIFO 0x21 /* Enable 64 bytes FIFO */ 126: #define FIFO_SIZE 64 /* FIFO size */ 127: #else 128: #define FC_FIFO 0x01 /* Enable FIFO */ 129: #define FIFO_SIZE 16 /* FIFO size */ 130: #endif 131: