| tkernel_2/driver/tef_em1d/sysdsk/src/ata.h | bare source | permlink (0.01 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * T-Kernel 2.0 Software Package 4: * 5: * Copyright 2011 by Ken Sakamura. 6: * This software is distributed under the latest version of T-License 2.x. 7: *---------------------------------------------------------------------- 8: * 9: * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17. 10: * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01. 11: * 12: *---------------------------------------------------------------------- 13: */ 14: 15: 16: /* 17: * ata.h System disk driver 18: * 19: * ATA (IDE) / ATAPI disk-related definition 20: */ 21: 22: /* 23: * Endian conversion 24: * !! Note that the data from ATA disk is the little endian !! 25: */ 26: Inline UH swapH(UH x) 27: { 28: return (x << 8) | (x >> 8); 29: } 30: Inline UW swapW(UW x) 31: { 32: return (UW)swapH((UH)x) << 16 | swapH((UH)(x >> 16)); 33: } 34: 35: #if BIGENDIAN 36: #define CnvLeH(x) ((UH)swapH((UH)(x))) 37: #define CnvLeW(x) ((UW)swapW((UW)(x))) 38: #define CnvBeH(x) (x) 39: #define CnvBeW(x) (x) 40: #else 41: #define CnvLeH(x) (x) 42: #define CnvLeW(x) (x) 43: #define CnvBeH(x) ((UH)swapH((UH)(x))) 44: #define CnvBeW(x) ((UW)swapW((UW)(x))) 45: #endif 46: 47: /* 48: * ATA disk physical block size : fixed 49: */ 50: #define ATA_SECSZ (512) /* Sector size */ 51: 52: /* 53: * Time-out (msec) 54: */ 55: #define TMO_ATACMD (10 * 1000) /* Command execution time-out */ 56: #define TMO_ATAPIREADY (10 * 1000) /* Ready time-out */ 57: 58: /* 59: * The maximum number of I/O sectors at one time 60: */ 61: #define MAX_IOSEC (256) /* The number of sectors at "ATA_SECSZ" */ 62: 63: /* 64: * ATA disk partition information 65: */ 66: #define N_PART 4 /* The number of partitions */ 67: 68: typedef struct { 69: UB BootInd; /* Boot indicator */ 70: UB StartHead; /* Start head number */ 71: UB StartSec; /* Start sector number */ 72: UB StartCyl; /* Start cylinder number */ 73: UB SysInd; /* System indicator */ 74: UB EndHead; /* End head number */ 75: UB EndSec; /* End sector number */ 76: UB EndCyl; /* End cylinder number */ 77: UW StartBlock; /* Relative start sector number */ 78: UW BlockCnt; /* The number of sectors */ 79: } PartTab; 80: 81: #define OFS_PART (446) /* Offset toward partition information */ 82: #define SIZE_PARTTAB (sizeof(PartTab) * N_PART) 83: #define OFS_SIGN (OFS_PART + SIZE_PARTTAB) 84: #define VALID_SIGN CnvLeH((UH)0xAA55) /* Signature */ 85: 86: /* 87: * ATA disk master boot block structure 88: * !! "PartTab[].StartBlock" in this structure doesn't match a word align, 89: * so cannot be directly used unchanged according to machines!! 90: */ 91: typedef struct { 92: UB BootCode[OFS_PART]; /* Code for boot(DOS/V) */ 93: PartTab Part[N_PART]; /* Partition information */ 94: UH Sign; /* Signature:0xAA55 */ 95: } MasterBoot; 96: 97: /* 98: * ATA command 99: */ 100: #define NOSET (-1) /* Unnecessary register setting */ 101: 102: #define ATA_IDENTIFY (0xEC) /* "IDENTIFY" command */ 103: #define ATA_READ (0x20) /* READ w. Retry command */ 104: #define ATA_WRITE (0x30) /* WRITE w. Retry command */ 105: 106: #define ATA_MREAD (0xC4) /* READ MULTIPLE command */ 107: #define ATA_MWRITE (0xC5) /* WRITE MULTIPLE command */ 108: #define ATA_SETMULTI (0xC6) /* SET MULTIPLE command */ 109: 110: /* 111: * ATA card setting information 112: */ 113: #define ATA_CNFIX (0x01) /* Continuous IO address */ 114: #define ATA_OFFIO2 (0x3F6 - 0x1F0) /* Offset toward IO 2 address */ 115: 116: /* 117: * IOConf[0] definition : The things execepting (*1)is valid only in the case of PC card 118: * All are 0 in the case of non PC card 119: * 120: * SSSS ABCD xxII IIII I: CONF INDEX 121: * A: ATAPI 0 = ATA 1 = ATAPI 122: * B: IO2 with or without 0 = with, 1 = without 123: * C: IO2 range 0 = 1 1 = 2 124: * D: IO1 range 0 = 8 1 = 16 125: * 126: */ 127: #define IOC_SPECIAL 0xF000 /* Special processing type */ 128: #define IOC_ATAPI 0x0800 /* ATAPI device */ 129: #define IOC_IO2_NONE 0x0400 /* here is no IO2 (*1) */ 130: #define IOC_IO2_2 0x0200 /* IO2 range 2 */ 131: #define IOC_IO1_16 0x0100 /* IO1 range 16 */ 132: #define IOC_CONFIX 0x003F /* Config index */ 133: 134: /* 135: * ATA I/O register address (Offset from base address) 136: */ 137: #define REG_DATA 0x00 /* Data (RW) */ 138: #define REG_FEATURE 0x01 /* Features (W) */ 139: #define REG_ERR 0x01 /* Error (R) */ 140: 141: #define REG_SECCNT 0x02 /* (ATA) Sector Count (RW) */ 142: #define REG_INTR 0x02 /* (ATAPI) Interrupt Reason(R) */ 143: 144: #define REG_SECNO 0x03 /* (ATA) Sector Number (RW) */ 145: 146: #define REG_CYL_L 0x04 /* (ATA) Cylinder Low (RW) */ 147: #define REG_CYL_H 0x05 /* (ATA) Cylinder High (RW) */ 148: 149: #define REG_BCNT_L 0x04 /* (ATAPI) Byte Count Low (RW) */ 150: #define REG_BCNT_H 0x05 /* (ATAPI) Byte Count High (RW) */ 151: 152: #define REG_DRVHEAD 0x06 /* Drive/Head (RW) */ 153: #define REG_CMD 0x07 /* Command (W) */ 154: #define REG_STS 0x07 /* Status (R) */ 155: 156: #define REG_ALTSTS 0x0E /* Alternate Status (R) */ 157: #define REG_DEVCTL 0x0E /* Device Control (W) */ 158: 159: #define REG_ALTSTS2 ATA_OFFIO2 /* Alternate Status (R) */ 160: #define REG_DEVCTL2 ATA_OFFIO2 /* Device Control (W) */ 161: 162: /* 163: I/O register: 7 6 5 4 3 2 1 0 164: (ATA) 165: 7:REG_STS BSY DRDY DF DSC DRQ CORR IDX ERR (R) 166: 6:REG_DRVHEAD 1 LBA 1 DRV HN3 HN2 HN1 HN0 (RW) 167: 1:REG_ERR (BBK)UNC MC IDNF MCR ABRT TK0 AMNF (R) 168: (MSC cmd) 0 WP MC 0 MCR 0 NM 0 (R) 169: 3x6:REG_DEVCTL x x x x 1 SRST ~IEN 0 (W) 170: 171: (ATAPI) 172: 7:REG_STS BSY DRDY DF DSC DRQ CORR x CHK (R) 173: 6:REG_DRVHEAD 1 x 1 DRV x x x x (RW) 174: 1:REG_ERR SK0 SK1 SK2 SK3 MCR ABRT EOM ILI (R) 175: 3x6:REG_DEVCTL x x x x 1 SRST ~IEN 0 (W) 176: 1:REG_FEATURE x x x x x x OVLP DMA (W) 177: 2:REG_INTR x x x x x REL IO Cod (R) 178: */ 179: 180: /* REG_STS */ 181: #define stBSY 0x80 182: #define stDRDY 0x40 183: #define stDF 0x20 184: #define stDSC 0x10 185: #define stDRQ 0x08 186: #define stCORR 0x04 187: #define stIDX 0x02 188: #define stERR 0x01 189: 190: /* REG_DRVHEAD */ 191: #define drDRV(n) (0xA0 | (((n) & 0x100) >> 4)) 192: #define drLBA 0x40 193: 194: /* REG_ERR */ 195: #define erMC 0x20 /* Media Change */ 196: #define erMCR 0x08 /* Media Change Request */ 197: #define erABRT 0x04 /* Command Abort */ 198: 199: #define erWP 0x40 /* Write Protect */ 200: #define erNM 0x02 /* No Midia */ 201: 202: /* REG_INTR */ 203: #define irIO 0x02 /* 0: Write, 1: Read */ 204: #define irCOD 0x01 /* 0: Data, 1: Command */ 205: 206: /* REG_DEVCTL */ 207: #define dcNORM (0x08) /* SRST = 0, ~IEN = 0 */ 208: #define dcSRST (0x08 | 0x04 | 0x02) /* SRST = 1, ~IEN = 1 */