gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      @(#)asm_depend.h (tk/EM1-D512)
   17:  *
   18:  *      Assembler Macro for EM1-D512
   19:  */
   20: 
   21: #ifndef __TK_ASM_DEPEND_H__
   22: #define __TK_ASM_DEPEND_H__
   23: 
   24: #define base(n)         ( (n) & 0xfffff000 )
   25: #define offs(n)         ( (n) & 0x00000fff )
   26: 
   27: /*
   28:  * Interrupt flag specified to CPS instruction
   29:  */
   30: #define IMASK           ai
   31: 
   32: /*
   33:  * Memory barrier instruction
   34:  *      .ISB Instruction Synchronization Barrier
   35:  *      .DSB Data Synchronization Barrier
   36:  *      .DMB Data Memory Barrier
   37:  */
   38:  .macro _mov reg, val
   39:    .ifnes "\reg", "\val"
   40:         mov    \reg, \val
   41:    .endif
   42:  .endm
   43:  .macro .ISB reg, val=#0
   44:         _mov   \reg, \val
   45:         mcr    p15, 0, \reg, cr7, c5, 4
   46:  .endm
   47:  .macro .DSB reg, val=#0
   48:         _mov   \reg, \val
   49:         mcr    p15, 0, \reg, cr7, c10, 4
   50:  .endm
   51:  .macro .DMB reg, val=#0
   52:         _mov   \reg, \val
   53:         mcr    p15, 0, \reg, cr7, c10, 5
   54:  .endm
   55: 
   56: /* ------------------------------------------------------------------------ */
   57: /*
   58:  *      Processing for returning from an exception
   59:  */
   60: 
   61: /*
   62:  * Processing for return from an interrupt (IRQ) (excluding FIQ)
   63:  */
   64:  .macro INT_RETURN
   65:         .arm
   66:         ldmfd  sp!, {r3, ip}
   67:         rfefd  sp!
   68:  .endm
   69: 
   70: /*
   71:  * Processing for return from an exception
   72:  */
   73:  .macro EXC_RETURN
   74:         .arm
   75:         ldmfd  sp!, {ip}
   76:         rfefd  sp!
   77:  .endm
   78: 
   79: /*
   80:  * Return from Exception/Interrupt (excluding FIQ)
   81:  */
   82:  .macro EIT_RETURN
   83:         .arm
   84:         mrs    ip, cpsr
   85:         and    ip, ip, #PSR_M(31)
   86:         cmp    ip, #PSR_IRQ
   87:         ldmeqfd        sp!, {r3, ip}          // for IRQ
   88:         ldmnefd        sp!, {ip}              // for other cases
   89:         rfefd  sp!
   90:  .endm
   91: 
   92: /* ------------------------------------------------------------------------ */
   93: /*
   94:  *      tk_ret_int()
   95:  */
   96: 
   97: /*
   98:  * enter SVC mode
   99:  */
  100:  .macro ENTER_SVC_MODE
  101:         .arm
  102:         cps    #PSR_SVC           // enter SVC mode
  103:  .endm
  104: 
  105: /*
  106:  * returning from handler using tk_ret_int()
  107:  *      mode handler exception mode (not usable for FIQ)
  108:  *
  109:  *      called from SVC mode
  110:  *
  111:  *      status of exception mode stack of the handler  when the macro is called
  112:  *              +---------------+
  113:  *      sp  ->       |R12=ip               |
  114:  *              |R14=lr             |
  115:  *              |SPSR               |
  116:  *              +---------------+
  117:  */
  118:  .macro TK_RET_INT mode
  119:         .arm
  120:         mov    ip, lr                             // ip = lr_svc
  121:         cpsid  IMASK, #\mode                    // return to the original exception
  122:         stmfd  sp!, {ip}                        // save lr_svc
  123:         svc    SWI_RETINT
  124:  .endm
  125: 
  126: /*
  127:  * returning from handler using tk_ret_int()
  128:  *      mode handler exception mode (not usable for FIQ)
  129:  *
  130:  *      called from SVC
  131:  *
  132:  *      status of exception mode stack of the handler  when the macro is called
  133:  *              +---------------+
  134:  *      sp  ->       |R3           |
  135:  *              |R12=ip             |
  136:  *              |R14=lr             |
  137:  *              |SPSR               |
  138:  *              +---------------+
  139:  */
  140:  .macro TK_RET_INT_FIQ mode
  141:         .arm
  142:         mov    r3, lr                             // r3 = lr_svc
  143:         cpsid  IMASK, #\mode                    // return to the original exception
  144:         swp    r3, r3, [sp]                       // save lr_svc, and restore r3
  145:         svc    SWI_RETINT
  146:  .endm
  147: 
  148: /* ------------------------------------------------------------------------ */
  149: /*
  150:  *      entry processing for a task exception handler
  151:  *
  152:  *              +---------------+
  153:  *      sp  ->       |texcd                | exception code
  154:  *              |PC         | return address from the handler
  155:  *              |CPSR               | CPSR to be restored on return
  156:  *              +---------------+
  157:  */
  158: 
  159:  .macro TEXHDR_ENTRY texhdr
  160:         .arm
  161:         swp    lr, lr, [sp]               // save lr , lr = texcd
  162:         stmfd  sp!, {r0-r4, ip} // save other registers
  163: 
  164:         mov    r4, sp
  165:         bic    sp, sp, #8-1               // align (module 8 bytes) of sp
  166: 
  167:         ldr    ip, =\texhdr
  168:         mov    r0, lr
  169:         blx    ip                 // call texhdr(texcd)
  170: 
  171:         mov    sp, r4
  172:         ldmfd  sp!, {r0-r4, ip, lr}     // restore registers
  173:         svc    SWI_RETTEX         // return from task exception handler
  174:  .endm
  175: 
  176: /* ------------------------------------------------------------------------ */
  177: #endif /* __TK_ASM_DEPEND_H__ */