| tkernel_2/include/tk/sysdepend/tef_em1d/sysdef_depend.h | bare source | permlink (0.03 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * T-Kernel 2.0 Software Package 4: * 5: * Copyright 2011 by Ken Sakamura. 6: * This software is distributed under the latest version of T-License 2.x. 7: *---------------------------------------------------------------------- 8: * 9: * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17. 10: * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01. 11: * 12: *---------------------------------------------------------------------- 13: */ 14: 15: /* 16: * @(#)sysdef_depend.h (tk/EM1-D512) 17: * 18: * Definition about EM1-D512 19: * 20: * Included also from assembler program. 21: */ 22: 23: #ifndef __TK_SYSDEF_DEPEND_H__ 24: #define __TK_SYSDEF_DEPEND_H__ 25: 26: /* 27: * Program Status Regsiter (PSR) 28: */ 29: #define PSR_N 0x80000000 /* conditional flag negative */ 30: #define PSR_Z 0x40000000 /* zero */ 31: #define PSR_C 0x20000000 /* carry */ 32: #define PSR_V 0x10000000 /* overflow */ 33: #define PSR_Q 0x08000000 /* Sticky overflow */ 34: #define PSR_GE 0x000f0000 /* SIMD >= flag */ 35: 36: #define PSR_J 0x01000000 /* Jazelle mode */ 37: #define PSR_IT 0x0600fc00 /* Thumb If-Then state */ 38: #define PSR_E 0x00000200 /* data endian */ 39: #define PSR_A 0x00000100 /* disable asynchronous abort */ 40: #define PSR_I 0x00000080 /* disable interrupt(IRQ) */ 41: #define PSR_F 0x00000040 /* disable fast interrupt(FIQ) */ 42: #define PSR_T 0x00000020 /* Thumb mode */ 43: 44: #define PSR_M(n) ( n ) /* processor mode 0-31 */ 45: #define PSR_USR PSR_M(16) /* user mode */ 46: #define PSR_FIQ PSR_M(17) /* fast interrupt(FIQ) mode */ 47: #define PSR_IRQ PSR_M(18) /* interrupt (IRQ) mode */ 48: #define PSR_SVC PSR_M(19) /* supervisor mode */ 49: #define PSR_ABT PSR_M(23) /* abort mode */ 50: #define PSR_UND PSR_M(27) /* undefined instruction mode */ 51: #define PSR_SYS PSR_M(31) /* system mode */ 52: 53: #define PSR_DI ( PSR_I|PSR_A ) /* disable (ordinary) interrupt */ 54: 55: /* 56: * task mode flag 57: * system wide (shared) taskmode 58: */ 59: #define TMF_CPL(n) ( (n) ) /* current protection level (0-3) */ 60: #define TMF_PPL(n) ( (n) << 16 ) /* previous protection level (0-3) */ 61: 62: /* 63: * system control coprocessor(CP15) : control register(CR1) 64: */ 65: #define CR1_M 0x0001 /* enable MMU */ 66: #define CR1_A 0x0002 /* enable alignment check */ 67: #define CR1_C 0x0004 /* enable (data) cache */ 68: #define CR1_W 0x0008 /* enable write buffer */ 69: #define CR1_B 0x0080 /* endian (1 - big endian) */ 70: #define CR1_S 0x0100 /* protect system */ 71: #define CR1_R 0x0200 /* protect ROM */ 72: #define CR1_SW 0x0400 /* enable SWP/SWPB */ 73: #define CR1_Z 0x0800 /* enable branch prediction */ 74: #define CR1_I 0x1000 /* enable instruction cache */ 75: #define CR1_V 0x2000 /* high vector */ 76: #define CR1_RR 0x4000 /* cache : prediction strategy (round robin) */ 77: #define CR1_L4 0x8000 /* ARMv4 compatible mode */ 78: 79: #define CR1_HA 0x00020000 /* hardware access flag */ 80: #define CR1_FI 0x00200000 /* fast interrupt */ 81: #define CR1_U 0x00400000 /* unalligned access */ 82: #define CR1_XP 0x00800000 /* subpage AP bit */ 83: #define CR1_VE 0x01000000 /* interrupt vector mechanism */ 84: #define CR1_EE 0x02000000 /* endian for exception processing */ 85: #define CR1_L2 0x04000000 /* enable L2 integrated cache */ 86: #define CR1_NMFI 0x08000000 /* enable non-maskable FIQ */ 87: #define CR1_TRE 0x10000000 /* enable TEX remap */ 88: #define CR1_AFE 0x20000000 /* enable access flag */ 89: #define CR1_TE 0x40000000 /* enable Thumb exception */ 90: 91: #define CR1_nF 0x40000000 /* clock mode (Fast) ARM920T */ 92: #define CR1_iA 0x80000000 /* clock mode (Async) ARM920T */ 93: 94: /* 95: * Fault Status(CP15:CR5) 96: * (v7) ARMv7 definition 97: */ 98: #define FSR_Alignment 0x1 /* 00x1 : misaligned access */ 99: #define FSR_BusErrorT 0xc /* 11x0 : bus error during address translation */ 100: #define FSR_Translation 0x5 /* 01x1 : missing page during address translation */ 101: #define FSR_Domain 0x9 /* 10x1 : domain access violation */ 102: #define FSR_Permission 0xd /* 11x1 : illegal access permission */ 103: #define FSR_BusErrorL 0x4 /* 01x0 : bus error during line fetch */ 104: #define FSR_BusErrorO 0x8 /* 10x0 : other bus errors */ 105: #define FSR_Section 0x0 /* xx0x : section */ 106: #define FSR_Page 0x2 /* xx1x : page */ 107: #define FSR_TypeMask 0xd /* type mask */ 108: 109: #define FSR_ICacheM 0x0004 /* 00100 : instruction cache management(v7) */ 110: #define FSR_AccessFlagS 0x0003 /* 00011 : access flag - section(v7) */ 111: #define FSR_AccessFlagP 0x0006 /* 00110 : access flag - page(v7) */ 112: #define FSR_DebugEvent 0x0002 /* 00010 : debug event (v7) */ 113: #define FSR_TypeMaskAll 0x140f /* type bit mask for all types(v7) */ 114: #define FSR_WnR 0x0800 /* 1=write/0=read(v7) */ 115: 116: /* 117: * memory barrier instruction 118: * ISB() Instruction Synchronization Barrier 119: * DSB() Data Synchronization Barrier 120: * DMB() Data Memory Barrier 121: */ 122: #define ISB() Asm("mcr p15, 0, %0, cr7, c5, 4":: "r"(0)) 123: #define DSB() Asm("mcr p15, 0, %0, cr7, c10, 4":: "r"(0)) 124: #define DMB() Asm("mcr p15, 0, %0, cr7, c10, 5":: "r"(0)) 125: 126: /* ------------------------------------------------------------------------ */ 127: 128: /* 129: * software interrupt number for T-Monitor 130: */ 131: #define SWI_MONITOR 4 /* T-Monitor service call */ 132: 133: /* 134: * software interrupt number for T-Kernel 135: */ 136: #define SWI_SVC 6 /* T-Kernel system call and extended SVC */ 137: #define SWI_RETINT 7 /* tk_ret_int() system call */ 138: #define SWI_DISPATCH 8 /* task dispatcher */ 139: #define SWI_DEBUG 9 /* debug support function */ 140: #define SWI_RETTEX 10 /* return from task exception */ 141: 142: /* 143: * software interrupt number for Extension 144: */ 145: #define SWI_KILLPROC 11 /* request to forcibly kill process */ 146: 147: #endif /* __TK_SYSDEF_DEPEND_H__ */