| tkernel_2/include/tk/sysdepend/tef_em1d/syslib_depend.h | bare source | permlink (0.01 seconds) |
1: /* 2: *---------------------------------------------------------------------- 3: * T-Kernel 2.0 Software Package 4: * 5: * Copyright 2011 by Ken Sakamura. 6: * This software is distributed under the latest version of T-License 2.x. 7: *---------------------------------------------------------------------- 8: * 9: * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17. 10: * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01. 11: * 12: *---------------------------------------------------------------------- 13: */ 14: 15: /* 16: * @(#)syslib_depend.h (tk/EM1-D512) 17: * 18: * T-Kernel/SM EM1-D512 Library 19: */ 20: 21: #ifndef __TK_SYSLIB_DEPEND_H__ 22: #define __TK_SYSLIB_DEPEND_H__ 23: 24: #include <tk/errno.h> 25: 26: #ifdef __cplusplus 27: extern "C" { 28: #endif 29: 30: /* 31: * CPU interrupt control 32: * intsts value of CPU CPSR register 33: * disint() set CPSR.I = 1, A = 1, and return the original CPSR value 34: * enaint() set CPSR.I,A = intsts.I,A. Other bits are unchanged. 35: * return the original CPSR value. 36: */ 37: IMPORT UINT disint( void ); 38: IMPORT UINT enaint( UINT intsts ); 39: #define DI(intsts) ( (intsts) = disint() ) 40: #define EI(intsts) ( enaint(intsts) ) 41: #define isDI(intsts) ( ((intsts) & 0x01c0) != 0 ) 42: 43: /* 44: * Interrupt vector 45: * interrupt vector is the index to the vector table. 46: */ 47: typedef UINT INTVEC; 48: 49: #define DINTNO(intvec) (intvec) /* convert to interrupt definition number */ 50: 51: /* 52: * value of interrupt vectors 53: */ 54: #define IV_IRQ(n) ( 32 + (n) ) /* IRQ interrupt 0-95 */ 55: #define IV_GPIO(n) ( 128 + (n) ) /* GPIO interrupt 0-127 */ 56: 57: /* 58: * interrupt controler 59: * intvec passed to the functions for interrupt controller must 60: * be within the valid IRQ and GPIO ranges above. 61: * If a value outside the valid range is passed, the subsequent 62: * correct behavior of the system is not guaranteed. 63: */ 64: 65: /* 66: * Set interrupt mode 67: * Set the interrupt mode specified by `intvec' to the mode given 68: * by `mode'. If an illegal mode is given, subsequent correct behavior 69: * of the system is not guaranteed. 70: * 71: * The case of IRQ 72: * mode := IM_ENA | IM_INV 73: * or IM_DIS 74: * 75: * The case of GPIO 76: * mode := IM_ENA | IM_LEVEL | (IM_HI || IM_LOW) | IM_ASYN 77: * or IM_ENA | IM_EDGE | (IM_HI || IM_LOW || IM_BOTH) | IM_ASYN 78: * or IM_DIS 79: * 80: * If IM_ENA is specified, the mode setting is done, and 81: * interrupt is disabled (DisableInt) and the interrupt pin is 82: * asserted. 83: * If IM_DIS is specified, interrupt pin is disasserted. 84: * Disasserted interrupt pin doesn't generate interrupt even if 85: * it is enabled (EnabledInt). 86: * In the initial state, pins are dis-asserted (IM_DIS). 87: * 88: * The initial status of the following interrupt controllers 89: * that manage GPIO interrupt is such that 90: * as if IM_ENA had been specified and interrupts are enabled 91: * (EnableInt). 92: * 93: * IRQ26 GIO6 Interrupt (GPIO port 96-111) 94: * IRQ27 GIO7 Interrupt (GPIO port 112-127) 95: * IRQ50 GIO0 Interrupt (GPIO port 0- 15) 96: * IRQ51 GIO1 Interrupt (GPIO port 16- 31) 97: * IRQ52 GIO2 Interrupt (GPIO port 32- 47) 98: * IRQ53 GIO3 Interrupt (GPIO port 48- 63) 99: * IRQ79 GIO4 Interrupt (GPIO port 64- 79) 100: * IRQ80 GIO5 Interrupt (GPIO port 80- 95) 101: */ 102: IMPORT void SetIntMode( INTVEC intvec, UINT mode ); 103: 104: #define IM_ENA 0x0001 /* interrupt pin enabled */ 105: #define IM_DIS 0x0000 /* interrupt pin disabled */ 106: #define IM_INV 0x0002 /* inverted logic */ 107: #define IM_LEVEL 0x0200 /* level */ 108: #define IM_EDGE 0x0000 /* edge */ 109: #define IM_HI 0x0000 /* high-level/leading-edge */ 110: #define IM_LOW 0x0100 /* low-level/trailing-edge */ 111: #define IM_BOTH 0x0400 /* both edge */ 112: #define IM_ASYN 0x0800 /* asynchronous */ 113: 114: /* 115: * Enable interrupt 116: * enable interrupt specified by intvec 117: */ 118: IMPORT void EnableInt( INTVEC intvec ); 119: 120: /* 121: * Disable interrupt 122: * disable interrupt specified by intvec 123: */ 124: IMPORT void DisableInt( INTVEC intvec ); 125: 126: /* 127: * Clear interrupt request 128: * clear the request of interrupt specified by intvec 129: * We need to clear the requests only in the case of edge-trigger interrupts. 130: */ 131: IMPORT void ClearInt( INTVEC intvec ); 132: 133: /* 134: * Check the existence of interrupt request 135: * check the existence of request for interrupt specified by intvec 136: * If there is, TRUE (non-zero value) is returned 137: * 138: * The existence of the request of interrupt is checked by 139: * 'raw' status register. 140: */ 141: IMPORT BOOL CheckInt( INTVEC intvec ); 142: 143: /* 144: * Issue EOI(End Of Interrupt) 145: */ 146: #define EndOfInt(intvec) 147: 148: /* ------------------------------------------------------------------------ */ 149: 150: /* 151: * I/O port access 152: * Only memory mapped I/O for Arm 153: */ 154: Inline void out_d( INT port, UD data ) 155: { 156: *(_UD*)port = data; 157: } 158: Inline void out_w( INT port, UW data ) 159: { 160: *(_UW*)port = data; 161: } 162: Inline void out_h( INT port, UH data ) 163: { 164: *(_UH*)port = data; 165: } 166: Inline void out_b( INT port, UB data ) 167: { 168: *(_UB*)port = data; 169: } 170: 171: Inline UD in_d( INT port ) 172: { 173: return *(_UD*)port; 174: } 175: Inline UW in_w( INT port ) 176: { 177: return *(_UW*)port; 178: } 179: Inline UH in_h( INT port ) 180: { 181: return *(_UH*)port; 182: } 183: Inline UB in_b( INT port ) 184: { 185: return *(_UB*)port; 186: } 187: 188: #ifdef __cplusplus 189: } 190: #endif 191: #endif /* __TK_SYSLIB_DEPEND_H__ */