gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      cache.c (EM1-D512)
   17:  *      Cache Operation
   18:  */
   19: 
   20: #include <basic.h>
   21: #include <tk/tkernel.h>
   22: #include <tk/sysdef.h>
   23: 
   24: #define CacheLineSZ     32
   25: 
   26: /*
   27:  * Obtain cache line size
   28:  */
   29: EXPORT INT GetCacheLineSize( void )
   30: {
   31:         return CacheLineSZ;
   32: }
   33: 
   34: /*
   35:  * Flush cache
   36:  *      Flush cache for an area that starts at laddr for len bytes.
   37:  *      cache is written back and invalidated.
   38:  *
   39:  *      mode := [TCM_ICACHE] | [TCM_DCACHE]
   40:  */
   41: EXPORT void FlushCacheM( CONST void *laddr, INT len, UINT mode )
   42: {
   43:         CONST VB       *p, *ep;
   44: 
   45:         ep = (VB*)laddr + len;
   46: 
   47:         if ( (mode & TCM_DCACHE) != 0 ) {
   48:                 p = (VB*)((UINT)laddr & ~(CacheLineSZ - 1));
   49:                 while ( p < ep ) {
   50:                         /* Clean and Invalidate data cache to PoC */
   51:                         Asm("mcr p15, 0, %0, cr7, c14, 1":: "r"(p));
   52:                         p += CacheLineSZ;
   53:                 }
   54:         }
   55:         if ( (mode & TCM_ICACHE) != 0 ) {
   56:                 p = (VB*)((UINT)laddr & ~(CacheLineSZ - 1));
   57:                 while ( p < ep ) {
   58:                         /* Invalidate instruction cache to PoC */
   59:                         Asm("mcr p15, 0, %0, cr7, c5,  1":: "r"(p));
   60:                         p += CacheLineSZ;
   61:                 }
   62:                 Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0));
   63:         }
   64:         DSB();
   65: }
   66: 
   67: EXPORT void FlushCache( CONST void *laddr, INT len )
   68: {
   69:         FlushCacheM(laddr, len, TCM_ICACHE|TCM_DCACHE);
   70: }
   71: 
   72: /*
   73:  * Control cache
   74:  *      mode := [CC_FLUSH] | [CC_INVALIDATE]
   75:  */
   76: EXPORT ER ControlCacheM( void *laddr, INT len, UINT mode )
   77: {
   78:         VB     *p, *ep;
   79: 
   80:         if ( (mode & ~(CC_FLUSH|CC_INVALIDATE)) != 0 ) return E_PAR;
   81: 
   82:         ep = (VB*)laddr + len;
   83: 
   84:         p = (VB*)((UINT)laddr & ~(CacheLineSZ - 1));
   85:         while ( p < ep ) {
   86:                 switch ( mode ) {
   87:                   case CC_FLUSH:
   88:                         /* Clean data cache to PoC */
   89:                         Asm("mcr p15, 0, %0, cr7, c10, 1":: "r"(p));
   90:                         break;
   91:                   case CC_INVALIDATE:
   92:                         /* Invalidate data cache to PoC */
   93:                         Asm("mcr p15, 0, %0, cr7, c6, 1":: "r"(p));
   94:                         break;
   95:                   default:
   96:                         /* Clean and Invalidate data cache to PoC */
   97:                         Asm("mcr p15, 0, %0, cr7, c14, 1":: "r"(p));
   98:                 }
   99: 
  100:                 /* Invalidate instruction cache to PoC */
  101:                 Asm("mcr p15, 0, %0, cr7, c5,  1":: "r"(p));
  102: 
  103:                 p += CacheLineSZ;
  104:         }
  105:         Asm("mcr p15, 0, %0, cr7, c5, 6":: "r"(0));
  106:         DSB();
  107: 
  108:         return E_OK;
  109: }