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14:
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19:
20: #ifndef _CPU_TASK_
21: #define _CPU_TASK_
22:
23: #include "cpu_insn.h"
24:
25: 26: 27:
28: typedef struct {
29: VW r[12];
30: UW taskmode;
31: void *usp;
32: void *lr_usr;
33: void *lr_svc;
34: VW ip;
35: void *pc;
36: VW spsr_svc;
37: } SStackFrame;
38:
39: 40: 41:
42: typedef struct {
43:
44: } UStackFrame;
45:
46: 47: 48: 49:
50: #define DORMANT_STACK_SIZE ( sizeof(VW) * 7 )
51:
52: 53: 54:
55: #define RESERVE_SSTACK(tskatr) 0
56:
57: 58: 59:
60: #if USE_MMU
61: #define INIT_PSR(rng) ( ( (rng) == 0 )? PSR_SVC: \
62: ( (rng) == 3 )? PSR_USR: PSR_SYS )
63: #else
64: #define INIT_PSR(rng) ( ( (rng) == 0 )? PSR_SVC: PSR_SYS )
65: #endif
66:
67: #define INIT_TMF(rng) ( TMF_PPL(rng) | TMF_CPL(rng) )
68:
69: 70: 71:
72: Inline void change_space( void *uatb, INT lsid )
73: {
74: UW ttbr;
75:
76:
77: Asm("mrc p15, 0, %0, cr2, c0, 1": "=r"(ttbr));
78: if ( uatb != NULL ) {
79: ttbr = (UW)uatb | (ttbr & 0x07f);
80: }
81:
82:
83: Asm("mcr p15, 0, %0, cr13, c0, 1":: "r"(0));
84: ISB();
85: Asm("mcr p15, 0, %0, cr2, c0, 0":: "r"(ttbr));
86: Asm("mcr p15, 0, %0, cr13, c0, 1":: "r"(lsid));
87: ISB();
88: }
89:
90: 91: 92: 93:
94: Inline void setup_context( TCB *tcb )
95: {
96: SStackFrame *ssp;
97: W rng;
98: UW pc, spsr;
99:
100: rng = (tcb->tskatr & TA_RNG3) >> 8;
101: ssp = tcb->isstack;
102: ssp--;
103:
104: spsr = INIT_PSR(rng);
105: pc = (UW)tcb->task;
106: if ( (pc & 1) != 0 ) {
107: spsr |= PSR_T;
108: }
109:
110:
111: ssp->taskmode = INIT_TMF(rng);
112: ssp->spsr_svc = spsr;
113: ssp->pc = (void*)(pc & ~0x00000001U);
114: tcb->tskctxb.ssp = ssp;
115: tcb->tskctxb.svc_ssp = NULL;
116:
117: if ( rng > 0 ) {
118: ssp->usp = tcb->istack;
119: }
120: }
121:
122: 123: 124: 125:
126: Inline void setup_stacd( TCB *tcb, INT stacd )
127: {
128: SStackFrame *ssp = tcb->tskctxb.ssp;
129:
130: ssp->r[0] = stacd;
131: ssp->r[1] = (VW)tcb->exinf;
132: }
133:
134: 135: 136:
137: Inline void cleanup_context( TCB *tcb )
138: {
139: }
140:
141: #endif