1: /*
2: *----------------------------------------------------------------------
3: * T-Kernel 2.0 Software Package
4: *
5: * Copyright 2011 by Ken Sakamura.
6: * This software is distributed under the latest version of T-License 2.x.
7: *----------------------------------------------------------------------
8: *
9: * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
10: * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
11: *
12: *----------------------------------------------------------------------
13: */
14:
15: /*
16: * icrt0_ram.S (EM1-D512)
17: * System Startup
18: */
19:
20: #include <machine.h>
21: #include <tk/asm.h>
22:
23: #if _Csym == 0
24: #define START _start
25: #else
26: #define START start
27: #endif
28:
29: /* Low level memory manager information */
30: .comm Csym(lowmem_top), 4 // Head of area (Low address)
31: .comm Csym(lowmem_limit), 4 // End of area (High address)
32:
33: .lcomm monitor_stacktop, 4 // Monitor stack pointer for re-startup
34:
35: #define SYSINFO 0x30004400 // System common information
36: #define RAM_TOP (SYSINFO + 0) // Head of ext. RAM free area
37: #define RAM_END (SYSINFO + 4) // End of ext. RAM free area
38: #define SYSCONF (SYSINFO + 8) // SYSCONF top
39:
40: .text
41: .balign 4
42: .globl START
43: .type START, %function
44: START:
45: /* Use the stack set by the monitor */
46: ldr ip, =PSR_SVC|PSR_DI|PSR_F // SVC mode/Interrupt disable
47: msr cpsr_xc, ip
48:
49: /* MMU is already ON. The initial setting is done.
50: Only cache should be ON */
51: mrc p15, 0, r4, cr1, c0
52: orr r4, r4, #CR1_C
53: orr r4, r4, #CR1_I|CR1_Z
54: mcr p15, 0, r4, cr1, c0
55: ldr r4, =0
56: mcr p15, 0, r4, cr7, c7, 0 // Cache flush
57:
58: ldr r5, =__data_org // Initialization of 'data' area (ROM startup)
59: ldr r6, =__data_start
60: subs r10, r5, r6 // If r10 != 0, start Rom
61: beq nocopy_data
62: ldr r7, =_edata
63: cmp r6, r7
64: bhs nocopy_data
65: copy_data:
66: ldr r4, [r5], #4
67: str r4, [r6], #4
68: cmp r6, r7
69: blo copy_data
70: nocopy_data:
71:
72: ldr r4, =0 // Clear 'bss' area
73: ldr r5, =__bss_start
74: ldr r6, =_end
75: cmp r5, r6
76: bhs nobss
77: clrbss:
78: str r4, [r5], #4
79: cmp r5, r6
80: blo clrbss
81: nobss:
82:
83: ldr ip, =monitor_stacktop // Monitor stack pointer for re-startup
84: str sp, [ip] // Save
85: bic sp, sp, #7 // align stack module 8 bytes
86:
87: ldr ip, =RAM_TOP // Low level memory manager initial setting
88: ldr r5, [ip]
89: cmp r6, r5 // _end or RAM_TOP
90: movhi r5, r6 // Either of High addresses
91: ldr ip, =lowmem_top
92: str r5, [ip] // lowmem_top = _end or RAM_TOP
93: ldr ip, =RAM_END
94: ldr r5, [ip]
95: ldr ip, =lowmem_limit
96: str r5, [ip] // lowmem_limit = RAM_END
97:
98: ldr r4, =SYSCONF
99: ldr r5, [r4]
100: cmp r5, #0
101: bleq l1
102:
103: cmp r10, #0
104: bleq l2
105:
106: l1:
107: bl Csym(ROM_startup) // Initialization at ROM startup
108:
109: l2:
110: bl Csym(main) // System startup
111:
112: l_end: // Not suppose to return from 'main,'
113: b l_end // but, just in case, prepare for out of control.