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    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      tkdev_conf.h (EM1-D512)
   17:  *      Target System Configuration
   18:  */
   19: 
   20: #ifndef _TKDEV_CONF_
   21: #define _TKDEV_CONF_
   22: /* Also included from assembler source */
   23: 
   24: /*
   25:  * Timer
   26:  *      register size  W
   27:  */
   28: #define TI(n)           ( 0xc0000000 + (n) )     /* TI0 */
   29: 
   30: #define TI_OP           TI(0x00) /* RW timer operation */
   31: #define TI_CLR          TI(0x04)        /* -W clear timer */
   32: #define TI_SET          TI(0x08)        /* RW set timer value */
   33: #define TI_RCR          TI(0x0c)        /* R- current counter */
   34: #define TI_SCLR         TI(0x14)       /* RW watch out for setting timer value */
   35: 
   36: #define TO_EN           0x0004           /* enable TOUT */
   37: #define TSTART          0x0002          /* start counting */
   38: #define TM_EN           0x0001           /* enable timer */
   39:  
   40: #define TCR_CLR         0x0002         /* clear counter */
   41: 
   42: #define TM_SCLR         0x0001         /* watch out for setting timer value */
   43: 
   44: /*
   45:  * Supply clock
   46:  *      register size W
   47:  */
   48: #define ASMU(n)         ( 0xc0110000 + (n) )
   49: 
   50: #define TI0TIN_SEL      ASMU(0x0138) /* set TI0/TW0 TIN */
   51: #define DIVTIMTIN       ASMU(0x014c)  /* set timer clock divisor */
   52: #define GCLKCTRL3       ASMU(0x01cc)  /* set clock gate */
   53: #define GCLKCTRL3ENA    ASMU(0x01d0)       /* enable write */
   54: 
   55: #define TITIN_PLL3      0            /* PLL3 divided by DIVTIMTIN */
   56: #define TITIN_32768     1           /* 32.768 KHz */
   57: #define TITIN_32K       2             /* 32 KHz */
   58: 
   59: #define TI0_TIN_GCK     0x00000001  /* TI0 TIN gate */
   60: 
   61: /*
   62:  * Input clock
   63:  *      PLL3 divided by DIVTIMTIN
   64:  */
   65: #define PLL3_CLK        229376000      /* Hz */
   66: 
   67: #define D0(d)           ( (d) & 0x7 )            /* DIV0TIMTIN */
   68: #define D1(d)           ( ((d) >> 4) & 0xf )     /* DIV1TIMTIN */
   69: 
   70: #define TIN_CLK(d)      ( PLL3_CLK / ((1 << D0(d)) * (D1(d) + 1)) )
   71: 
   72: /*
   73:  * TI0 timer interrupt
   74:  */
   75: #define IRQ_TIMER       54                    /* IRQ number */
   76: #define VECNO_TIMER     ( EIT_IRQ(IRQ_TIMER) )      /* interrupt vector number */
   77: 
   78: #define IRQM(irq)       ( 1 << ((irq) % 32) ) /* IRQ bit mask */
   79: 
   80: /*
   81:  * Interrupt controller
   82:  *      register size W
   83:  */
   84: #define AINT(n)         ( 0xc0020000 + (n) )   /* ACPU Interrupt */
   85: #define SINT(n)         ( 0xcc010000 + (n) )   /* ACPU Secure Interrupt */
   86: 
   87: #define IT0_IEN0        AINT(0x0000)   /* RW ACPU interrupt enable  0 */
   88: #define IT0_IEN1        AINT(0x0004)   /* RW ACPU interrupt enable 1 */
   89: #define IT0_IEN2        AINT(0x0100)   /* RW ACPU interrupt enable 2 */
   90: #define IT0_IDS0        AINT(0x0008)   /* -W ACPU interrupt disable 0 */
   91: #define IT0_IDS1        AINT(0x000C)   /* -W ACPU interrupt disable 1 */
   92: #define IT0_IDS2        AINT(0x0104)   /* -W ACPU interrupt disable 2 */
   93: #define IT0_RAW0        AINT(0x0010)   /* R- ACPU interrupt Raw status 0 */
   94: #define IT0_RAW1        AINT(0x0014)   /* R- ACPU interrupt Raw status 1 */
   95: #define IT0_RAW2        AINT(0x0108)   /* R- ACPU interrupt Raw status 2 */
   96: #define IT0_MST0        AINT(0x0018)   /* R- ACPU interrupt mask / status 0 */
   97: #define IT0_MST1        AINT(0x001C)   /* R- ACPU interrupt mask / status 1 */
   98: #define IT0_MST2        AINT(0x010C)   /* R- ACPU interrupt mask / status 2 */
   99: #define IT0_IIR         AINT(0x0024)   /* -W ACPU interrupt status / reset */
  100: #define IT0_FIE         AINT(0x0080)   /* RW ACPU FIQ enable interrupt */
  101: #define IT0_FID         AINT(0x0084)   /* -W ACPU FIQ disable interrupt */
  102: #define IT_PINV_SET0    AINT(0x0300)       /* RW enable inverted logic for interrupt input 0 */
  103: #define IT_PINV_SET1    AINT(0x0304)       /* RW enable inverted logic for interrupt input 1 */
  104: #define IT_PINV_SET2    AINT(0x0308)       /* RW enable inverted logic for interrupt input 2 */
  105: #define IT_PINV_CLR0    AINT(0x0310)       /* -W disable inverted logic for interrupt input 0 */
  106: #define IT_PINV_CLR1    AINT(0x0314)       /* -W disable inverted logic for interrupt input 1 */
  107: #define IT_PINV_CLR2    AINT(0x0318)       /* -W disable inverted logic for interrupt input 2 */
  108: #define IT_LIIS         AINT(0x0320)   /* -W internal interrupt status / set */
  109: #define IT_LIIR         AINT(0x0324)   /* -W internal interrupt status / reset */
  110: 
  111: #define IT0_IENS0       SINT(0xE200)  /* RW ACPU Secure enable interrupt 0 */
  112: #define IT0_IENS1       SINT(0xE204)  /* RW ACPU Secure enable interrupt 1 */
  113: #define IT0_IENS2       SINT(0xE208)  /* RW ACPU Secure enable interrupt 2 */
  114: #define IT0_IDSS0       SINT(0xE20C)  /* -W ACPU Secure disable interrupt 0 */
  115: #define IT0_IDSS1       SINT(0xE210)  /* -W ACPU Secure disable interrupt 1 */
  116: #define IT0_IDSS2       SINT(0xE214)  /* -W ACPU Secure disable interrupt 2 */
  117: 
  118: /*
  119:  * GIO interrupt
  120:  *  register size  W
  121:  */
  122: #define GIO(b, n)       ( (b) + (n) )         /* General I/O */
  123: #define _L              ( 0xc0050000 + 0x000 )
  124: #define _H              ( 0xc0050000 + 0x040 )
  125: #define _HH             ( 0xc0050000 + 0x080 )
  126: #define _HHH            ( 0xc0050000 + 0x200 )
  127: 
  128: #define GIO_IIA(b)      GIO(b,0x0014)        /* RW enable interrupt ??? */
  129: #define GIO_IEN(b)      GIO(b,0x0018)        /* -W enable interrupt */
  130: #define GIO_IDS(b)      GIO(b,0x001C)        /* -W disable interrupt */
  131: #define GIO_IIM(b)      GIO(b,0x001C)        /* R- enable interrupt ??? */
  132: #define GIO_RAW(b)      GIO(b,0x0020)        /* R- interrupt Raw status */
  133: #define GIO_MST(b)      GIO(b,0x0024)        /* R- interrupt mask / status */
  134: #define GIO_IIR(b)      GIO(b,0x0028)        /* -W reset the cause of interrupt */
  135: #define GIO_GSW(b)      GIO(b,0x003C)        /* RW connected to GIO_INT_FIQ pin */
  136: #define GIO_IDT(n,b)    GIO(b,0x0100+(n)*4) /* RW interrupt detection method  0-3 */
  137: #define GIO_RAWBL(b)    GIO(b,0x0110)      /* R- edge-triggered interrupt status L */
  138: #define GIO_RAWBH(b)    GIO(b,0x0114)      /* R- edge-triggered interrupt status H */
  139: #define GIO_IRBL(b)     GIO(b,0x0118)       /* -W clear the cause of edge-triggered interrupt L */
  140: #define GIO_IRBH(b)     GIO(b,0x011C)       /* -W clear the cause of edge-tirggered interrupt H */
  141: 
  142: /*
  143:  * Timer interrupt level
  144:  *      No meaning since EM1-D512 does not have a mechanism of prioritized interrupt.
  145:  */
  146: #define TIMER_INTLEVEL          0
  147: 
  148: #endif /* _TKDEV_CONF_ */