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23:
24: #include "sysdepend.h"
25: #include <arm/em1d512.h>
26:
27:
28: IMPORT ER initSIO_ns16550(SIOCB *, const CFGSIO *, W speed);
29: IMPORT ER initMemDisk(DISKCB *, const CFGDISK *);
30:
31:
32: EXPORT MEMSEG MemSeg[] = {
33:
34: {0x10000000, 0x30000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
35:
36: {0x30000000, 0x40000000, MSA_RAM, PGA_RW|PGA_C},
37:
38: {0x40000000, 0x70000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
39:
40: {0x70000000, 0x72000000, MSA_FROM, PGA_RO|PGA_C |0x90000000},
41:
42: {0xa0000000, 0xb0000000, MSA_SRAM, PGA_RW|PGA_NC},
43:
44: {0xb0000000, 0xd0000000, MSA_IO, PGA_RW|PGA_D |PGA_S|PGA_XN},
45:
46: {0xf0000000, 0xffffffff, MSA_ROM, PGA_RO|PGA_NC},
47:
48: {0x70000000, 0x70020000, MSA_MON, 0},
49: {0x70030000, 0x72000000, MSA_RDA, 0},
50: {0x30006000, 0x34000000, MSA_OS, 0},
51: };
52:
53: EXPORT W N_MemSeg = sizeof(MemSeg) / sizeof(MEMSEG);
54:
55:
56: EXPORT MEMSEG NoMemSeg[] = {
57: {0x00000000, 0x10000000, 0, 0},
58: {0x72000000, 0xa0000000, 0, 0},
59: {0xd0000000, 0xf0000000, 0, 0},
60: };
61:
62: EXPORT W N_NoMemSeg = sizeof(NoMemSeg) / sizeof(MEMSEG);
63:
64: 65: 66: 67:
68: EXPORT const CFGSIO ConfigSIO[] = {
69: {initSIO_ns16550, 0},
70: };
71:
72: EXPORT const W N_ConfigSIO = sizeof(ConfigSIO) / sizeof(CFGSIO);
73:
74:
75: 76: 77: 78:
79: EXPORT const CFGDISK ConfigDisk[] = {
80: {"rda", DA_RONLY, initMemDisk, 0},
81: };
82:
83: EXPORT const W N_ConfigDisk = sizeof(ConfigDisk) / sizeof(CFGDISK);
84:
85:
86: EXPORT const UH BootSignature = 0xe382;
87: EXPORT UB * const PBootAddr = (UB *)0x30200000;
88:
89:
90:
91: #define IICC_IICE (1 << 7)
92: #define IICC_WREL (1 << 5)
93: #define IICC_WTIM (1 << 3)
94: #define IICC_ACKE (1 << 2)
95: #define IICC_STT (1 << 1)
96: #define IICC_SPT (1 << 0)
97:
98: #define IICCL_SMC (1 << 3)
99: #define IICCL_DFC (1 << 2)
100:
101: #define IICSE_MSTS (1 << 15)
102: #define IICSE_ALD (1 << 14)
103: #define IICSE_ACKD (1 << 10)
104: #define IICSE_SPD (1 << 8)
105:
106: #define IICF_IICBSY (1 << 6)
107: #define IICF_STCEN (1 << 1)
108: #define IICF_IICRSV (1 << 0)
109:
110: #define IIC_TOPDATA (1 << 11)
111: #define IIC_LASTDATA (1 << 10)
112:
113: #define TIMEOUT 1000000
114:
115: #define IIC2_IRQ 39
116: #define IRQbit(x) (1 << ((x) % 32))
117:
118:
119: LOCAL ER wait_state(UW addr, UW mask, UW value)
120: {
121: W i;
122:
123: for (i = TIMEOUT; i > 0; i--) {
124: waitUsec(1);
125: if ((in_w(addr) & mask) == value) break;
126: }
127:
128: return i ? E_OK : E_TMOUT;
129: }
130:
131:
132: LOCAL void clear_int(void)
133: {
134: out_w(IT0_IIR, IRQbit(IIC2_IRQ));
135: return;
136: }
137:
138:
139: LOCAL void setup_int(void)
140: {
141: out_w(IT_PINV_CLR1, IRQbit(IIC2_IRQ));
142: out_w(IT0_IENS1, IRQbit(IIC2_IRQ));
143: clear_int();
144: return;
145: }
146:
147:
148: LOCAL ER wait_int(void)
149: {
150: ER er;
151:
152: er = wait_state(IT0_RAW1, IRQbit(IIC2_IRQ), IRQbit(IIC2_IRQ));
153: clear_int();
154:
155: return er;
156: }
157:
158:
159: LOCAL ER send_start(UB addr)
160: {
161: ER er;
162: UW sts;
163:
164:
165: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
166: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_STT);
167:
168:
169: er = wait_state(IIC_IICSE(IIC2), IICSE_MSTS, IICSE_MSTS);
170: if (er < E_OK) goto fin0;
171:
172:
173: out_w(IIC_IIC(IIC2), addr);
174: er = wait_int();
175: if (er < E_OK) goto fin0;
176:
177:
178: sts = in_w(IIC_IICSE(IIC2));
179: if ((sts & IICSE_ALD) || !(sts & IICSE_ACKD)) {
180: er = E_IO;
181: goto fin0;
182: }
183:
184: er = E_OK;
185: fin0:
186: return er;
187: }
188:
189:
190: LOCAL ER send_stop(void)
191: {
192: ER er;
193:
194:
195: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_SPT);
196:
197:
198: er = wait_state(IIC_IICSE(IIC2), IICSE_SPD, IICSE_SPD);
199:
200: return er;
201: }
202:
203:
204: LOCAL ER send_data(UB data)
205: {
206: ER er;
207: UW sts;
208:
209:
210: out_w(IIC_IIC(IIC2), data);
211: er = wait_int();
212: if (er < E_OK) goto fin0;
213:
214:
215: sts = in_w(IIC_IICSE(IIC2));
216: if (!(sts & IICSE_ACKD)) {
217: er = E_IO;
218: goto fin0;
219: }
220:
221: er = E_OK;
222: fin0:
223: return er;
224: }
225:
226:
227: LOCAL W recv_data(W attr)
228: {
229: W er;
230:
231:
232: if (attr & IIC_TOPDATA) {
233: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_WTIM);
234: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_ACKE);
235: }
236:
237:
238: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
239: er = wait_int();
240: if (er < E_OK) goto fin0;
241:
242:
243: er = in_w(IIC_IIC(IIC2)) & 0xff;
244: fin0:
245:
246: if ((attr & IIC_LASTDATA) || er < E_OK) {
247: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WTIM);
248: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) & ~IICC_ACKE);
249: out_w(IIC_IICC(IIC2), in_w(IIC_IICC(IIC2)) | IICC_WREL);
250: wait_int();
251: }
252:
253: return er;
254: }
255:
256:
257: LOCAL ER iic_start(void)
258: {
259: ER er;
260:
261:
262: out_w(IIC_IICC(IIC2), 0);
263: out_w(IIC_IICCL(IIC2), IICCL_SMC | IICCL_DFC);
264: out_w(IIC_IICF(IIC2), IICF_STCEN | IICF_IICRSV);
265: out_w(IIC_IICC(IIC2), IICC_IICE | IICC_WTIM);
266: clear_int();
267:
268:
269: er = wait_state(IIC_IICF(IIC2), IICF_IICBSY, 0);
270:
271: return er;
272: }
273:
274:
275: LOCAL void iic_finish(void)
276: {
277: out_w(IIC_IICC(IIC2), 0);
278: return;
279: }
280:
281:
282: LOCAL W IICGPIORead(W addr)
283: {
284: W dat;
285:
286: setup_int();
287:
288: iic_start();
289: send_start(addr);
290: dat = recv_data(IIC_TOPDATA | IIC_LASTDATA);
291: send_stop();
292: iic_finish();
293:
294: clear_int();
295:
296: return dat;
297: }
298:
299:
300: LOCAL void IICGPIOWrite(W addr, W dat)
301: {
302: setup_int();
303:
304: iic_start();
305: send_start(addr);
306: send_data(dat);
307: send_stop();
308: iic_finish();
309:
310: clear_int();
311:
312: return;
313: }
314:
315:
316:
317: IMPORT W pmicRead(W reg);
318: IMPORT W pmicWrite(W reg, W dat);
319: #define pmicDelay(x) waitUsec(4)
320: #define USBPowerOn 0xe0
321: #define USBPowerOff 0xe0
322:
323:
324: EXPORT UW DipSwStatus(void)
325: {
326: UW d;
327:
328:
329: d = IICGPIORead(0xd9);
330:
331:
332: d = (d ^ SW_MON) & SW_MON;
333:
334:
335: if (in_w(GIO_I(GIO_L)) & 0x00000100) d |= SW_ABT;
336:
337: return d;
338: }
339:
340:
341: EXPORT void usbPower(BOOL power)
342: {
343: pmicWrite(27, (pmicRead(27) & 0x0f) |
344: (power ? USBPowerOn : USBPowerOff));
345: pmicDelay();
346: }
347:
348:
349: EXPORT void powerOff(void)
350: {
351: W i;
352:
353: for (i = 10; i < 14; i++) pmicWrite(i, 0xff);
354: pmicDelay();
355:
356: for (i = 5 ; i < 9; i++) pmicWrite(i, 0xff);
357: pmicDelay();
358:
359: while (1) {
360: pmicWrite(15, 0x60);
361: pmicDelay();
362: }
363: }
364:
365:
366: EXPORT void resetStart(void)
367: {
368: while (1) {
369:
370: pmicWrite(15, 0xac);
371: pmicDelay();
372: }
373: }
374:
375:
376: EXPORT void initHardware(void)
377: {
378:
379: out_w(GIO_IDT1(GIO_L), 0x00000008);
380: out_w(GIO_IIR(GIO_L), 0x00000100);
381: out_w(GIO_IIA(GIO_L), 0x00000100);
382: out_w(GIO_IEN(GIO_L), 0x00000100);
383:
384: return;
385: }
386:
387:
388: EXPORT void cpuLED(UW v)
389: {
390: UB m, d, r, c;
391:
392: m = ~((v >> 16) | 0xf0);
393: d = ~((v >> 0) | 0xf0);
394: r = IICGPIORead(0xb9);
395: c = (r ^ d) & m;
396: IICGPIOWrite(0xb8, r ^ c);
397: }
398:
399: 400: 401: 402: 403: 404: 405:
406: EXPORT W procHwInt(UW vec)
407: {
408:
409: if (vec != EIT_GPIO(8)) return 0;
410:
411:
412: out_w(GIO_IIR(GIO_L), 0x00000100);
413:
414: DSP_S("Abort Switch (SW1) Pressed");
415: return 1;
416: }
417:
418:
419:
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559: EXPORT const UW GPIOConfig[] __attribute__((section(".startup"))) = {
560: CHG_PINSEL_G(0),
561: 0x55400C00,
562: CHG_PINSEL_G(16),
563: 0x55555555,
564: CHG_PINSEL_G(32),
565: 0x54555055,
566:
567:
568:
569: CHG_CTRL_AB0_BOOT,
570: 0x00000001,
571:
572: CHG_PINSEL_G(48),
573: 0x55555555,
574: CHG_PINSEL_G(64),
575: 0xffc05555,
576: CHG_PINSEL_G(80),
577: 0x06556940,
578:
579: CHG_PINSEL_G(96),
580: 0x55555555,
581: CHG_PINSEL_G(112),
582: 0x00000555,
583: CHG_PINSEL_SP0,
584: 0x00000000,
585: CHG_PINSEL_DTV,
586: 0x00000001,
587: CHG_PINSEL_SD0,
588: 0x00000000,
589: CHG_PINSEL_SD1,
590: 0x00000002,
591: CHG_PINSEL_IIC2,
592: 0x00000000,
593: CHG_PULL_G(0),
594: 0x55055005,
595: CHG_PULL_G(8),
596: 0x00000005,
597: CHG_PULL_G(16),
598: 0x00000000,
599: CHG_PULL_G(24),
600: 0x00000000,
601: CHG_PULL_G(32),
602: 0x00550000,
603: CHG_PULL_G(40),
604: 0x00050000,
605: CHG_PULL_G(48),
606: 0x11111111,
607: CHG_PULL_G(56),
608: 0x11111111,
609: CHG_PULL_G(64),
610: 0x11111111,
611: CHG_PULL_G(72),
612: 0x00000005,
613: CHG_PULL_G(80),
614: 0x00400050,
615:
616: CHG_PULL_G(88),
617: 0x55000444,
618:
619: CHG_PULL_G(96),
620: 0x44444444,
621: CHG_PULL_G(104),
622: 0x04044444,
623:
624: CHG_PULL_G(112),
625: 0x00000000,
626: CHG_PULL_G(120),
627: 0x00000000,
628:
629: CHG_PULL(0),
630: 0x50000004,
631:
632: CHG_PULL(1),
633: 0x15110600,
634:
635:
636:
637:
638:
639:
640: CHG_PULL(2),
641: 0x60000661,
642:
643:
644:
645: CHG_PULL(3),
646: 0x00000000,
647:
648: GIO_E0(GIO_L),
649: 0x000001d9,
650: GIO_E1(GIO_L),
651: 0x00000604,
652: GIO_E0(GIO_H),
653: 0x00001030,
654: GIO_E1(GIO_H),
655: 0x00000000,
656: GIO_E0(GIO_HH),
657: 0xc0020100,
658: GIO_E1(GIO_HH),
659: 0x00040200,
660: GIO_OL(GIO_L),
661: 0x06040000,
662: GIO_OL(GIO_HH),
663: 0x02000000,
664: GIO_OH(GIO_HH),
665: 0x00040000,
666:
667: 0x00000000,
668: 0x00000000,
669: };