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    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      cpuctrl2.S
   17:  *
   18:  *       ARM CPU control
   19:  *
   20:  *       Assume that system control processor (CP15) exists.
   21:  */
   22: #define _in_asm_source_
   23: 
   24: #include <machine.h>
   25: #include <tk/sysdef.h>
   26: 
   27: #define DCACHE_NWAY             4  /* N as in the number of N-way data cache */
   28: #define DCACHE_NWAY_SHIFT       30
   29: #define DCACHE_NSEG             256        /* number of segments of data cache */
   30: #define DCACHE_NSEG_SHIFT       5
   31: 
   32: /*
   33:  * flush the entire cache (write back and then invalidate)
   34:  *      void FlushCache( void )
   35:  */
   36:         .text
   37:         .balign        4
   38:         .globl Csym(FlushCache)
   39:         .type  Csym(FlushCache), %function
   40: Csym(FlushCache):
   41:         ldr    r2, =DCACHE_NWAY-1
   42:   l_flush_dcache1:
   43:         ldr    r3, =DCACHE_NSEG-1
   44:   l_flush_dcache2:
   45:         mov    ip, r2, lsl #DCACHE_NWAY_SHIFT
   46:         orr    ip, ip, r3, lsl #DCACHE_NSEG_SHIFT
   47:         mcr    p15, 0, ip, cr7, c14, 2            // data cache is written back,
   48:         subs   r3, r3, #1                        // and is invalidated
   49:         bpl    l_flush_dcache2
   50:         subs   r2, r2, #1
   51:         bpl    l_flush_dcache1
   52: 
   53:         ldr    ip, =0
   54:         mcr    p15, 0, ip, cr7, c7, 0             // Invalidate I/D-Cache
   55:         mcr    p15, 0, ip, cr7, c10, 4            // Drain Write Buffer
   56: 
   57:         bx     lr
   58: 
   59: /*
   60:  * cache and MMU control
   61:  *      void setCacheMMU( UW cp15r1 )
   62:  */
   63:         .text
   64:         .balign        4
   65:         .globl Csym(setCacheMMU)
   66:         .type  Csym(setCacheMMU), %function
   67: Csym(setCacheMMU):
   68:         stmfd  sp!, {r4, lr}                    // save registers
   69:         mov    r4, r0                             // save argument
   70: 
   71:         /* flush cache */
   72:         bl     Csym(FlushCache)
   73: 
   74:         /* TLB flush */
   75:         ldr    ip, =0
   76:         mcr    p15, 0, ip, cr8, c7, 0             // Invalidate I/D-TLB
   77: 
   78:         /* set new r1 for CP15 */
   79:         mrc    p15, 0, r2, cr1, cr0, 0
   80:         ldr    r3, =0x3307                        // V,I,R,S,C,A,M (B = 0)
   81:         and    r0, r4, r3
   82:         mvn    r3, r3                             // clear old V,I,R,S,C,A,M
   83:         and    r2, r2, r3
   84:         orr    r0, r0, r2
   85:         mcr    p15, 0, r0, cr1, cr0, 0
   86:         nop
   87:         nop
   88: 
   89:         ldmfd  sp!, {r4, lr}                    // restore registers
   90:         bx     lr