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    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      memattr.S
   17:  *
   18:  *       manipulation of page table
   19:  */
   20: #define _in_asm_source_
   21: 
   22: #include <machine.h>
   23: #include <tk/sysdef.h>
   24: 
   25: #include "setup_em1d512.h"
   26: 
   27: /*
   28:  * memory barrier macros
   29:  */
   30: .macro _mov reg, val
   31:   .ifnes "\reg", "\val"
   32:         mov    \reg, \val
   33:   .endif
   34: .endm
   35: .macro .ISB reg, val=#0
   36:         _mov   \reg, \val
   37:         mcr    p15, 0, \reg, cr7, c5, 4
   38: .endm
   39: .macro .DSB reg, val=#0
   40:         _mov   \reg, \val
   41:         mcr    p15, 0, \reg, cr7, c10, 4
   42: .endm
   43: .macro .DMB reg, val=#0
   44:         _mov   \reg, \val
   45:         mcr    p15, 0, \reg, cr7, c10, 5
   46: .endm
   47: 
   48: /*
   49:  * change memory attribute
   50:  *      void ChangeMemAttr(UW top, UW end, UW attr)
   51:  *               change the memory attribute of memory area from `top' to `end' - 1 into `attr'
   52:  *               The physical address where T-Monitor resides is assumed to start at 0x00000000.
   53:  *               It must be called with disabled cache.
   54:  */
   55:         .text
   56:         .balign        4
   57:         .globl Csym(ChangeMemAttr)
   58:         .type  Csym(ChangeMemAttr), %function
   59: Csym(ChangeMemAttr):
   60: changememattr_start:
   61:         stmfd  sp!, {r4, r5, r7, r9, r10}
   62: 
   63:         /* Map T-Monitor to 0x00000000 and up, the information before the mapping is saved. */
   64:         ldr    ip, =PAGETBL_BASE
   65:         ldr    r4, [ip]
   66:         ldr    r10, =attr_prev
   67:         str    r4, [r10]
   68:         ldr    r4, =0x00009402            // Strongly-order, Kernel/RO
   69:         str    r4, [ip]
   70: 
   71:         .DSB   r4
   72:         mcr    p15, 0, r4, cr8, cr7, 0            // I/D TLB invalidate
   73:         mcr    p15, 0, r4, cr7, cr5, 6            // invalidate BTC
   74:         .DSB   r4
   75:         .ISB   r4
   76: 
   77:         /* Jump to the address into the remapped area */
   78:         ldr    r4, =changememattr_main
   79:         ldr    r9, =0xfff00000
   80:         bic    r4, r4, r9         // r4 &= 0x000fffff
   81:         mov    pc, r4
   82: 
   83:         .pool
   84: 
   85: changememattr_main:     
   86:         bic    r2, r2, r9         // r2 &= 0x000fffff
   87:         mov    r4, r0, lsr #20
   88:         add    r4, ip, r4, lsl #2 // r4 = (r2 >> 20) * 4 + PAGETBL_BASE
   89: 
   90: changememattr_loop:
   91:         ldr    r5, [r4]           // *r4 = (*r4 & 0xfff00000) | r2
   92:         and    r5, r5, r9
   93:         orr    r5, r5, r2
   94:         str    r5, [r4], #4
   95:         add    r0, r0, #0x00100000
   96:         cmp    r0, r1
   97:         bne    changememattr_loop
   98: 
   99:         /* Jump to the address in the originally mapped area */
  100:         .DSB   r4
  101:         mcr    p15, 0, r4, cr8, cr7, 0            // I/D TLB invalidate
  102:         mcr    p15, 0, r4, cr7, cr5, 6            // invalidate BTC
  103:         .DSB   r4
  104:         .ISB   r4
  105: 
  106:         ldr    pc, =changememattr_finish
  107: 
  108:         .pool
  109: 
  110: changememattr_finish:
  111:         /* Unmap the T-Monitor in the area from 0x00000000 and up. */
  112:         ldr    r4, [r10]                  // attr_prev
  113:         str    r4, [ip]                   // PAGETBL_BASE
  114: 
  115:         .DSB   r4
  116:         mcr    p15, 0, r4, cr8, cr7, 0            // I/D TLB invalidate
  117:         mcr    p15, 0, r4, cr7, cr5, 6            // invalidate BTC
  118:         .DSB   r4
  119:         .ISB   r4
  120: 
  121:         ldmfd  sp!, {r4, r5, r7, r9, r10}
  122:         bx     lr
  123: 
  124:         .pool
  125: 
  126: 
  127:         .bss
  128: attr_prev:
  129:         .long  0