gonzui

    1: /*
    2:  *----------------------------------------------------------------------
    3:  *    T-Kernel 2.0 Software Package
    4:  *
    5:  *    Copyright 2011 by Ken Sakamura.
    6:  *    This software is distributed under the latest version of T-License 2.x.
    7:  *----------------------------------------------------------------------
    8:  *
    9:  *    Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
   10:  *    Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
   11:  *
   12:  *----------------------------------------------------------------------
   13:  */
   14: 
   15: /*
   16:  *      cpudepend.h
   17:  *
   18:  *       ARM-related definitions
   19:  */
   20: 
   21: #ifndef __MONITOR_ARM_CPUDEPEND_H__
   22: #define __MONITOR_ARM_CPUDEPEND_H__
   23: 
   24: #include <machine.h>
   25: 
   26: /*
   27:  * monitor stack area
   28:  * stack area is from     &__stack_top to &__stack_bottom
   29:  *       initial stack pointer = &__stack_bottom
   30:  */
   31: IMPORT UB       __stack_top, __stack_bottom;
   32: 
   33: /*
   34:  * first level page table
   35:  */
   36: IMPORT UW* const        TopPageTable;  /* location of page table */
   37: #define N_PageTableEntry        0x1000 /* number of entries */
   38: 
   39: /*
   40:  * address conversion to non-cached and cached area
   41:  *      in the case of ARM, all address have the same cache mode, and hence
   42:  *       return as it is.
   43:  */
   44: #define NOCACHE_ADDR(p)         (p)
   45: #define CACHE_ADDR(p)           (p)
   46: 
   47: /*
   48:  * I/O port access functions
   49:  */
   50: Inline void out_w( INT port, UW data )
   51: {
   52:         *(_UW*)port = data;
   53: }
   54: Inline void out_h( INT port, UH data )
   55: {
   56:         *(_UH*)port = data;
   57: }
   58: Inline void out_b( INT port, UB data )
   59: {
   60:         *(_UB*)port = data;
   61: }
   62: 
   63: Inline UW in_w( INT port )
   64: {
   65:         return *(_UW*)port;
   66: }
   67: Inline UH in_h( INT port )
   68: {
   69:         return *(_UH*)port;
   70: }
   71: Inline UB in_b( INT port )
   72: {
   73:         return *(_UB*)port;
   74: }
   75: 
   76: /*
   77:  * value of control register (r1) of system control coprocessor cp15
   78:  */
   79: #if CPU_ARM1176
   80: #define MASK_CACHEMMU   (0xFFFFCC78)              /* V,I,R,S,C,A,M (B = 0)   */
   81: #define VALID_CACHEMMU  (0x3307)         /* B = 0                  */
   82: #define DIS_CACHEMMU    (0x0000)           /* I=0,R=0,S=0,C=0,A=0,M=0 */
   83: #define DIS_CACHEONLY   (0x0001)          /* I=0,R=0,S=0,C=0,A=0,M=1 */
   84: #define ENB_CACHEMMU    (0x1007)           /* I=1,R=0,S=0,C=1,A=1,M=1 */
   85: #define ENB_MMUONLY     (0x0003)            /* I=0,R=0,S=0,C=0,A=1,M=1 */
   86: #endif
   87: 
   88: /*
   89:  * references registers under monitor control
   90:  *       references the value of registers at the time of monitor entry.
   91:  */
   92: IMPORT UW getCP15( W reg, W opcd );     /* CP15 register CRn: reg, Op2: opcd */
   93: IMPORT UW getCurPCX( void );    /* PC register (raw value) */
   94: IMPORT UW getCurCPSR( void );   /* CPSR register */
   95: 
   96: #endif /* __MONITOR_ARM_CPUDEPEND_H__ */