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23: #ifndef __MONITOR_ARM_EM1D_H__
24: #define __MONITOR_ARM_EM1D_H__
25:
26: #include <tk/sysdef.h>
27:
28: #define AB0Base 0x2fff0000
29: #define AB0_FLASHCOMSET (AB0Base + 0x0000)
30: #define AB0_FLASHCOMLATCH (AB0Base + 0x0004)
31: #define AB0_FLASHCOMADD0 (AB0Base + 0x0010)
32: #define AB0_FLASHCOMDATA0 (AB0Base + 0x0014)
33: #define AB0_FLASHCOMADD1 (AB0Base + 0x0018)
34: #define AB0_FLASHCOMDATA1 (AB0Base + 0x001c)
35: #define AB0_FLASHCLKCTRL (AB0Base + 0x0080)
36: #define AB0_FLA_RCLK_DLY (AB0Base + 0x0084)
37: #define AB0_WAIT_STATUS (AB0Base + 0x0090)
38: #define AB0_CSnBASEADD(n) (AB0Base + 0x0100 + 0x0010 * (n))
39: #define AB0_CSnBITCOMP(n) (AB0Base + 0x0104 + 0x0010 * (n))
40: #define AB0_CSnWAITCTRL(n) (AB0Base + 0x0200 + 0x0020 * (n))
41: #define AB0_CSnWAITCTRL_W(n) (AB0Base + 0x0204 + 0x0020 * (n))
42: #define AB0_CSnREADCTRL(n) (AB0Base + 0x0208 + 0x0020 * (n))
43: #define AB0_CSnWAIT_MASK(n) (AB0Base + 0x020c + 0x0020 * (n))
44: #define AB0_CSnCONTROL(n) (AB0Base + 0x0210 + 0x0020 * (n))
45: #define AB0_CSnFLASHRCR(n) (AB0Base + 0x0214 + 0x0020 * (n))
46: #define AB0_CSnFLASHWCR(n) (AB0Base + 0x0218 + 0x0020 * (n))
47: #define AB0_CSnWAITCTRL2(n) (AB0Base + 0x0300 + 0x0020 * (n))
48: #define AB0_CSnWAITCTRL_W2(n) (AB0Base + 0x0304 + 0x0020 * (n))
49: #define AB0_CSnREADCTRL2(n) (AB0Base + 0x0308 + 0x0020 * (n))
50: #define AB0_CSnWAIT_MASK2(n) (AB0Base + 0x030c + 0x0020 * (n))
51: #define AB0_CSnCONTROL2(n) (AB0Base + 0x0310 + 0x0020 * (n))
52: #define AB0_CSnFLASHRCR2(n) (AB0Base + 0x0314 + 0x0020 * (n))
53: #define AB0_CSnFLASHWCR2(n) (AB0Base + 0x0318 + 0x0020 * (n))
54:
55: #define LCDBase 0x40270000
56: #define LCD_CONTROL (LCDBase + 0x0000)
57: #define LCD_QOS (LCDBase + 0x0004)
58: #define LCD_DATAREQ (LCDBase + 0x0008)
59: #define LCD_LCDOUT (LCDBase + 0x0010)
60: #define LCD_BUSSEL (LCDBase + 0x0014)
61: #define LCD_STATUS (LCDBase + 0x0018)
62: #define LCD_BACKCOLOR (LCDBase + 0x001c)
63: #define LCD_AREAADR (LCDBase + 0x0020)
64: #define LCD_HOFFSET (LCDBase + 0x0024)
65: #define LCD_IFORMAT (LCDBase + 0x0028)
66: #define LCD_RESIZE (LCDBase + 0x002c)
67: #define LCD_HTOTAL (LCDBase + 0x0030)
68: #define LCD_HAREA (LCDBase + 0x0034)
69: #define LCD_HEDGE1 (LCDBase + 0x0038)
70: #define LCD_HEDGE2 (LCDBase + 0x003c)
71: #define LCD_VTOTAL (LCDBase + 0x0040)
72: #define LCD_VAREA (LCDBase + 0x0044)
73: #define LCD_VEDGE1 (LCDBase + 0x0048)
74: #define LCD_VEDGE2 (LCDBase + 0x004c)
75: #define LCD_INTSTATUS (LCDBase + 0x0060)
76: #define LCD_INTRAWSTATUS (LCDBase + 0x0064)
77: #define LCD_INTENSET (LCDBase + 0x0068)
78: #define LCD_INTENCLR (LCDBase + 0x006c)
79: #define LCD_INTFFCLR (LCDBase + 0x0070)
80: #define LCD_FRAMECNT (LCDBase + 0x0074)
81:
82: #define UARTnBase(n) (0x50000000 + 0x00010000 * (n))
83: #define UART0 0x00
84: #define UART1 0x01
85: #define UART2 0x02
86:
87:
88: #define SDIxBase(x) (0x50050000 + 0x00010000 * (x))
89: #define SDIA 0x00
90: #define SDIB 0x01
91: #define SDIC 0x04
92: #define SDIx_CMD(x) (SDIxBase(x) + 0x0000)
93: #define SDIx_PORT(x) (SDIxBase(x) + 0x0004)
94: #define SDIx_ARG0(x) (SDIxBase(x) + 0x0008)
95: #define SDIx_ARG1(x) (SDIxBase(x) + 0x000c)
96: #define SDIx_STOP(x) (SDIxBase(x) + 0x0010)
97: #define SDIx_SECCNT(x) (SDIxBase(x) + 0x0014)
98: #define SDIx_RSP0(x) (SDIxBase(x) + 0x0018)
99: #define SDIx_RSP1(x) (SDIxBase(x) + 0x001c)
100: #define SDIx_RSP2(x) (SDIxBase(x) + 0x0020)
101: #define SDIx_RSP3(x) (SDIxBase(x) + 0x0024)
102: #define SDIx_RSP4(x) (SDIxBase(x) + 0x0028)
103: #define SDIx_RSP5(x) (SDIxBase(x) + 0x002c)
104: #define SDIx_RSP6(x) (SDIxBase(x) + 0x0030)
105: #define SDIx_RSP7(x) (SDIxBase(x) + 0x0034)
106: #define SDIx_INFO1(x) (SDIxBase(x) + 0x0038)
107: #define SDIx_INFO2(x) (SDIxBase(x) + 0x003c)
108: #define SDIx_INFO1_MASK(x) (SDIxBase(x) + 0x0040)
109: #define SDIx_INFO2_MASK(x) (SDIxBase(x) + 0x0044)
110: #define SDIx_CLK_CTRL(x) (SDIxBase(x) + 0x0048)
111: #define SDIx_SIZE(x) (SDIxBase(x) + 0x004c)
112: #define SDIx_OPTION(x) (SDIxBase(x) + 0x0050)
113: #define SDIx_ERR_STS1(x) (SDIxBase(x) + 0x0058)
114: #define SDIx_ERR_STS2(x) (SDIxBase(x) + 0x005c)
115: #define SDIx_BUF0(x) (SDIxBase(x) + 0x0060)
116: #define SDIx_SDIO_MODE(x) (SDIxBase(x) + 0x0068)
117: #define SDIx_SDIO_INFO1(x) (SDIxBase(x) + 0x006c)
118: #define SDIx_SDIO_INFO1_MASK(x) (SDIxBase(x) + 0x0070)
119: #define SDIx_CC_EXT_MODE(x) (SDIxBase(x) + 0x01b0)
120: #define SDIx_SOFT_RST(x) (SDIxBase(x) + 0x01c0)
121: #define SDIx_VERSION(x) (SDIxBase(x) + 0x01c4)
122: #define SDIx_USER(x) (SDIxBase(x) + 0x0200)
123: #define SDIx_USER2(x) (SDIxBase(x) + 0x0204)
124: #define SDIx_DMA(x) (SDIxBase(x) + 0x0300)
125:
126: #define AB1Base 0x50070000
127: #define AB1_ERROR (AB1Base + 0x0000)
128: #define AB1_GENERAL (AB1Base + 0x0004)
129: #define AB1_DEBUG0 (AB1Base + 0x0008)
130:
131: #define USBBase 0x60000000
132:
133:
134: #define TimerBase(x) (0xc0000000 + 0x00000100 * (x))
135: #define TI0 0x00
136: #define TI1 0x01
137: #define TI2 0x02
138: #define TI3 0x03
139: #define TW0 0x10
140: #define TW1 0x11
141: #define TW2 0x12
142: #define TW3 0x13
143: #define TG0 0x20
144: #define TG1 0x21
145: #define TG2 0x22
146: #define TG3 0x23
147: #define TG4 0x24
148: #define TG5 0x25
149: #define Txx_OP(x) (TimerBase(x) + 0x0000)
150: #define Txx_CLR(x) (TimerBase(x) + 0x0004)
151: #define Txx_SET(x) (TimerBase(x) + 0x0008)
152: #define Txx_RCR(x) (TimerBase(x) + 0x000c)
153: #define Txx_SCLR(x) (TimerBase(x) + 0x0014)
154:
155: #define AINTBase 0xc0020000
156: #define IT0_IEN0 (AINTBase + 0x0000)
157: #define IT0_IEN1 (AINTBase + 0x0004)
158: #define IT0_IDS0 (AINTBase + 0x0008)
159: #define IT0_IDS1 (AINTBase + 0x000c)
160: #define IT0_RAW0 (AINTBase + 0x0010)
161: #define IT0_RAW1 (AINTBase + 0x0014)
162: #define IT0_MST0 (AINTBase + 0x0018)
163: #define IT0_MST1 (AINTBase + 0x001c)
164: #define IT0_IIR (AINTBase + 0x0024)
165: #define IT0_IPI3_SET (AINTBase + 0x003c)
166: #define IT3_IPI0_CLR (AINTBase + 0x005c)
167: #define IT0_FIE (AINTBase + 0x0080)
168: #define IT0_FID (AINTBase + 0x0084)
169: #define IT0_IEN2 (AINTBase + 0x0100)
170: #define IT0_IDS2 (AINTBase + 0x0104)
171: #define IT0_RAW2 (AINTBase + 0x0108)
172: #define IT0_MST2 (AINTBase + 0x010c)
173: #define IT_PINV_SET0 (AINTBase + 0x0300)
174: #define IT_PINV_SET1 (AINTBase + 0x0304)
175: #define IT_PINV_SET2 (AINTBase + 0x0308)
176: #define IT_PINV_CLR0 (AINTBase + 0x0310)
177: #define IT_PINV_CLR1 (AINTBase + 0x0314)
178: #define IT_PINV_CLR2 (AINTBase + 0x0318)
179: #define IT0_LIIS (AINTBase + 0x0320)
180: #define IT0_LIIR (AINTBase + 0x0324)
181: #define IT3_IEN0 (AINTBase + 0xc000)
182: #define IT3_IEN1 (AINTBase + 0xc004)
183: #define IT3_IDS0 (AINTBase + 0xc008)
184: #define IT3_IDS1 (AINTBase + 0xc00c)
185: #define IT3_RAW0 (AINTBase + 0xc010)
186: #define IT3_RAW1 (AINTBase + 0xc014)
187: #define IT3_MST0 (AINTBase + 0xc018)
188: #define IT3_MST1 (AINTBase + 0xc01c)
189: #define IT3_IIR (AINTBase + 0xc024)
190: #define IT3_IPI0_SET (AINTBase + 0xc030)
191: #define IT0_IPI3_CLR (AINTBase + 0xc050)
192: #define ID_VBS (AINTBase + 0xc090)
193: #define ID_CLR (AINTBase + 0xc094)
194: #define IT3_IEN2 (AINTBase + 0xc100)
195: #define IT3_IDS2 (AINTBase + 0xc104)
196: #define IT3_RAW2 (AINTBase + 0xc108)
197: #define IT3_MST2 (AINTBase + 0xc10c)
198:
199: #define ASINTBase 0xcc010000
200: #define IT0_IENS0 (ASINTBase + 0xe200)
201: #define IT0_IENS1 (ASINTBase + 0xe204)
202: #define IT0_IENS2 (ASINTBase + 0xe208)
203: #define IT0_IDSS0 (ASINTBase + 0xe20c)
204: #define IT0_IDSS1 (ASINTBase + 0xe210)
205: #define IT0_IDSS2 (ASINTBase + 0xe214)
206:
207: #define GIOBase(x) (0xc0050000 + 0x00000040 * (x))
208: #define GIO_L 0x00
209: #define GIO_H 0x01
210: #define GIO_HH 0x02
211: #define GIO_HHH 0x08
212: #define GIO_E1(x) (GIOBase(x) + 0x0000)
213: #define GIO_E0(x) (GIOBase(x) + 0x0004)
214: #define GIO_EM(x) (GIOBase(x) + 0x0004)
215: #define GIO_OL(x) (GIOBase(x) + 0x0008)
216: #define GIO_OH(x) (GIOBase(x) + 0x000c)
217: #define GIO_I(x) (GIOBase(x) + 0x0010)
218: #define GIO_IIA(x) (GIOBase(x) + 0x0014)
219: #define GIO_IEN(x) (GIOBase(x) + 0x0018)
220: #define GIO_IDS(x) (GIOBase(x) + 0x001c)
221: #define GIO_IIM(x) (GIOBase(x) + 0x001c)
222: #define GIO_RAW(x) (GIOBase(x) + 0x0020)
223: #define GIO_MST(x) (GIOBase(x) + 0x0024)
224: #define GIO_IIR(x) (GIOBase(x) + 0x0028)
225: #define GIO_GSW(x) (GIOBase(x) + 0x003c)
226: #define GIO_IDT0(x) (GIOBase(x) + 0x0100)
227: #define GIO_IDT1(x) (GIOBase(x) + 0x0104)
228: #define GIO_IDT2(x) (GIOBase(x) + 0x0108)
229: #define GIO_IDT3(x) (GIOBase(x) + 0x010c)
230: #define GIO_RAWBL(x) (GIOBase(x) + 0x0110)
231: #define GIO_RAWBH(x) (GIOBase(x) + 0x0114)
232: #define GIO_IRBL(x) (GIOBase(x) + 0x0118)
233: #define GIO_IRBH(x) (GIOBase(x) + 0x011c)
234:
235: #define MEMCBase 0xc00a0000
236: #define MEMC_CACHE_MODE (MEMCBase + 0x0000)
237: #define MEMC_DEGFUN (MEMCBase + 0x0008)
238: #define MEMC_INTSTATUS_A (MEMCBase + 0x0014)
239: #define MEMC_INTRAWSTATUS_A (MEMCBase + 0x0018)
240: #define MEMC_INTENSET_A (MEMCBase + 0x001c)
241: #define MEMC_INTENCLR_A (MEMCBase + 0x0020)
242: #define MEMC_INTFFCLR_A (MEMCBase + 0x0024)
243: #define MEMC_ERRMID (MEMCBase + 0x0068)
244: #define MEMC_ERRADR (MEMCBase + 0x006c)
245: #define MEMC_REQSCH (MEMCBase + 0x1000)
246: #define MEMC_DDR_CONFIGF (MEMCBase + 0x2000)
247: #define MEMC_DDR_CONFIGA1 (MEMCBase + 0x2004)
248: #define MEMC_DDR_CONFIGA2 (MEMCBase + 0x2008)
249: #define MEMC_DDR_CONFIGC1 (MEMCBase + 0x200c)
250: #define MEMC_DDR_CONFIGC2 (MEMCBase + 0x2010)
251: #define MEMC_DDR_CONFIGR1 (MEMCBase + 0x2014)
252: #define MEMC_DDR_CONFIGR2 (MEMCBase + 0x2018)
253: #define MEMC_DDR_CONFIGR3 (MEMCBase + 0x201c)
254: #define MEMC_DDR_CONFIGT1 (MEMCBase + 0x2020)
255: #define MEMC_DDR_CONFIGT2 (MEMCBase + 0x2024)
256: #define MEMC_DDR_CONFIGT3 (MEMCBase + 0x2028)
257: #define MEMC_DDR_STATE8 (MEMCBase + 0x202c)
258:
259: #define PMUBase 0xc0100000
260: #define PMU_PC (PMUBase + 0x0004)
261: #define PMU_START (PMUBase + 0x0008)
262: #define PMU_POWER_ON_PC (PMUBase + 0x0030)
263: #define PMU_WDT_COUNT_EN (PMUBase + 0x0060)
264: #define PMU_WDT_COUNT_LMT (PMUBase + 0x0064)
265: #define PMU_INT_HANDLER_PC (PMUBase + 0x0068)
266: #define PMU_PSR (PMUBase + 0x0070)
267: #define PMU_TRIG_STATUS (PMUBase + 0x0074)
268: #define PMU_REGA (PMUBase + 0x0078)
269: #define PMU_REGB (PMUBase + 0x007c)
270: #define PMU_INTSTATUS_A (PMUBase + 0x0080)
271: #define PMU_INTRAWSTATUS_A (PMUBase + 0x0084)
272: #define PMU_INTENSET_A (PMUBase + 0x0088)
273: #define PMU_INTENCLR_A (PMUBase + 0x008c)
274: #define PMU_INTFFCLR_A (PMUBase + 0x0090)
275: #define PMU_PCERR (PMUBase + 0x00a8)
276: #define PMU_CMD_BUF_RAM (PMUBase + 0x1000)
277: #define PMU_CMD_BUF_FF (PMUBase + 0x2000)
278:
279: #define ASMUBase 0xc0110000
280: #define RESETCTRL0 (ASMUBase + 0x0000)
281: #define RESETREQ0 (ASMUBase + 0x0004)
282: #define RESETREQ0ENA (ASMUBase + 0x0008)
283: #define RESETREQ1 (ASMUBase + 0x000c)
284: #define RESETREQ1ENA (ASMUBase + 0x0010)
285: #define RESETREQ2 (ASMUBase + 0x0018)
286: #define RESETREQ2ENA (ASMUBase + 0x001c)
287: #define WDT_INT_RESET (ASMUBase + 0x0020)
288: #define RESET_PCLK_COUNT (ASMUBase + 0x0024)
289: #define AUTO_MODE_EN (ASMUBase + 0x007c)
290: #define CLK_MODE_SEL (ASMUBase + 0x0080)
291: #define PLL1CTRL0 (ASMUBase + 0x0084)
292: #define PLL1CTRL1 (ASMUBase + 0x0088)
293: #define PLL2CTRL0 (ASMUBase + 0x008c)
294: #define PLL2CTRL1 (ASMUBase + 0x0090)
295: #define PLL3CTRL0 (ASMUBase + 0x0094)
296: #define PLL3CTRL1 (ASMUBase + 0x0098)
297: #define PLLLOCKTIME (ASMUBase + 0x009c)
298: #define AUTO_PLL_STANDBY (ASMUBase + 0x00a8)
299: #define PLLVDDWAIT (ASMUBase + 0x00b4)
300: #define CLKSTOPSIG_ST (ASMUBase + 0x00c4)
301: #define CLK32_STATUS (ASMUBase + 0x00c8)
302: #define POWER_RECORD (ASMUBase + 0x00cc)
303: #define ASMU_INT_STATUS (ASMUBase + 0x00d0)
304: #define ASMU_INT_RAW_STATUS (ASMUBase + 0x00d4)
305: #define ASMU_INT_ENSET (ASMUBase + 0x00d8)
306: #define ASMU_INT_ENCLR (ASMUBase + 0x00dc)
307: #define ASMU_INT_ENMON (ASMUBase + 0x00e0)
308: #define ASMU_INT_CLEAR (ASMUBase + 0x00e4)
309: #define NORMALA_DIV (ASMUBase + 0x00f0)
310: #define NORMALB_DIV (ASMUBase + 0x00f4)
311: #define NORMALC_DIV (ASMUBase + 0x00f8)
312: #define NORMALD_DIV (ASMUBase + 0x00fc)
313: #define ECONOMY_DIV (ASMUBase + 0x0100)
314: #define STANDBY_DIV (ASMUBase + 0x0104)
315: #define POWERON_DIV (ASMUBase + 0x0108)
316: #define DIVSP0SCLK (ASMUBase + 0x0118)
317: #define DIVSP1SCLK (ASMUBase + 0x011c)
318: #define DIVSP2SCLK (ASMUBase + 0x0120)
319: #define DIVMEMCRCLK (ASMUBase + 0x0128)
320: #define DIVCAMSCLK (ASMUBase + 0x012c)
321: #define DIVLCDLCLK (ASMUBase + 0x0130)
322: #define DIVIICSCLK (ASMUBase + 0x0134)
323: #define TI0TIN_SEL (ASMUBase + 0x0138)
324: #define TI1TIN_SEL (ASMUBase + 0x013c)
325: #define TI2TIN_SEL (ASMUBase + 0x0140)
326: #define TI3TIN_SEL (ASMUBase + 0x0144)
327: #define TIGnTIN_SEL (ASMUBase + 0x0148)
328: #define DIVTIMTIN (ASMUBase + 0x014c)
329: #define DIVMWISCLK (ASMUBase + 0x0150)
330: #define DIVDMATCLK (ASMUBase + 0x0154)
331: #define DIVU70SCLK (ASMUBase + 0x0158)
332: #define DIVU71SCLK (ASMUBase + 0x015c)
333: #define DIVU72SCLK (ASMUBase + 0x0160)
334: #define DIVPM0SCLK (ASMUBase + 0x016c)
335: #define DIVPM1SCLK (ASMUBase + 0x0170)
336: #define DIVREFCLK (ASMUBase + 0x0178)
337: #define DIVPWMPWCLK (ASMUBase + 0x0184)
338: #define AHBCLKCTRL0 (ASMUBase + 0x01a0)
339: #define AHBCLKCTRL1 (ASMUBase + 0x01a4)
340: #define APBCLKCTRL0 (ASMUBase + 0x01a8)
341: #define APBCLKCTRL1 (ASMUBase + 0x01ac)
342: #define CLKCTRL (ASMUBase + 0x01b0)
343: #define GCLKCTRL0 (ASMUBase + 0x01b4)
344: #define GCLKCTRL0ENA (ASMUBase + 0x01b8)
345: #define GCLKCTRL1 (ASMUBase + 0x01bc)
346: #define GCLKCTRL1ENA (ASMUBase + 0x01c0)
347: #define GCLKCTRL2 (ASMUBase + 0x01c4)
348: #define GCLKCTRL2ENA (ASMUBase + 0x01c8)
349: #define GCLKCTRL3 (ASMUBase + 0x01cc)
350: #define GCLKCTRL3ENA (ASMUBase + 0x01d0)
351: #define AUTO_FRQ_CHANGE (ASMUBase + 0x01dc)
352: #define AUTO_FRQ_MASK0 (ASMUBase + 0x01e0)
353: #define AUTO_FRQ_MASK1 (ASMUBase + 0x01e4)
354: #define DFS_HALFMODE (ASMUBase + 0x01e8)
355: #define FLA_CLK_DLY (ASMUBase + 0x01f0)
356: #define MEMCCLK270_SEL (ASMUBase + 0x01fc)
357: #define ASMU_BGCTRL (ASMUBase + 0x0208)
358: #define QR_ENA (ASMUBase + 0x0220)
359: #define QR_CLKDIV (ASMUBase + 0x0224)
360: #define FAKE_MODE (ASMUBase + 0x0238)
361: #define POWERSW_STATUS (ASMUBase + 0x023c)
362: #define POWERSW_ENA (ASMUBase + 0x0240)
363: #define L1_POWERSW (ASMUBase + 0x0244)
364: #define ACPU_POWERSW (ASMUBase + 0x0248)
365: #define ADSP_POWERSW (ASMUBase + 0x024c)
366: #define ACPU_BUB (ASMUBase + 0x0254)
367: #define ADSP_BUB (ASMUBase + 0x0258)
368: #define POWERSW_ACTRL_EN (ASMUBase + 0x025c)
369: #define LOG1SW_ACTRL (ASMUBase + 0x0260)
370: #define ADSPSW_ACTRL (ASMUBase + 0x0264)
371: #define L1_BUZ (ASMUBase + 0x0268)
372: #define L1_BUZ2 (ASMUBase + 0x026c)
373: #define ACPUBUFTYPE (ASMUBase + 0x0288)
374: #define ADSPUBUFTYPE (ASMUBase + 0x028c)
375: #define HXBBUFTYPE (ASMUBase + 0x0290)
376: #define STATUS_RECORD(n) (ASMUBase + 0x0320 + 0x004 *(n))
377: #define ACPU_INIT (ASMUBase + 0x0360)
378: #define AB1_U70WAITCTRL (ASMUBase + 0x03c0)
379: #define AB1_U71WAITCTRL (ASMUBase + 0x03c4)
380: #define AB1_U72WAITCTRL (ASMUBase + 0x03c8)
381: #define AB1_IIC2WAITCTRL (ASMUBase + 0x03cc)
382: #define AB1_IICWAITCTRL (ASMUBase + 0x03d0)
383: #define AB1_U70READCTRL (ASMUBase + 0x03d4)
384: #define AB1_U71READCTRL (ASMUBase + 0x03d8)
385: #define AB1_U72READCTRL (ASMUBase + 0x03dc)
386: #define AB1_IIC2READCTRL (ASMUBase + 0x03e0)
387: #define AB1_IICREADCTRL (ASMUBase + 0x03e4)
388: #define AB1_SDIBWAITCTRL (ASMUBase + 0x03e8)
389: #define AB1_SDIBREADCTRL (ASMUBase + 0x03ec)
390: #define AB1_SDICWAITCTRL (ASMUBase + 0x03f0)
391: #define AB1_SDICREADCTRL (ASMUBase + 0x03f4)
392: #define FLASHCLK_CTRL (ASMUBase + 0x0494)
393: #define L2_POWERSW_BUZ (ASMUBase + 0x0500)
394: #define LOG2SW_ACTRLEN (ASMUBase + 0x0504)
395: #define LOG2SW_ACTRL (ASMUBase + 0x0508)
396: #define L3_POWERSW_BUZ (ASMUBase + 0x050c)
397: #define LOG3SW_ACTRLEN (ASMUBase + 0x0510)
398: #define LOG3SW_ACTRL (ASMUBase + 0x0514)
399: #define PLL_STATUS (ASMUBase + 0x0520)
400: #define IO_L0_LM_BUZ (ASMUBase + 0x0814)
401: #define RESETREQ3 (ASMUBase + 0x083c)
402: #define RESETREQ3ENA (ASMUBase + 0x0840)
403: #define APBCLKCTRL2 (ASMUBase + 0x0848)
404: #define GCLKCTRL4 (ASMUBase + 0x084c)
405: #define GCLKCTRL4ENA (ASMUBase + 0x0850)
406: #define AUTO_FRQ_MASK3 (ASMUBase + 0x0860)
407: #define DFS_FIFOMODE (ASMUBase + 0x0864)
408: #define DFS_FIFO_REQMASK (ASMUBase + 0x0868)
409: #define LCD_FIFOTHRESHOLD (ASMUBase + 0x086c)
410: #define CAM_FIFOTHRESHOLD (ASMUBase + 0x0870)
411: #define CAM_SAFE_RESET (ASMUBase + 0x0878)
412: #define DTV_SAFE_RESET (ASMUBase + 0x0880)
413: #define USB_SAFE_RESET (ASMUBase + 0x0884)
414: #define CLKCTRL1 (ASMUBase + 0x088c)
415: #define AB1_SDIAWAITCTRL (ASMUBase + 0x0890)
416: #define AB1_SDIAREADCTRL (ASMUBase + 0x0894)
417: #define MEMC_HAND_SHAKE_FAKE (ASMUBase + 0x08a0)
418: #define SEL_BIGWEST (ASMUBase + 0x08b8)
419:
420: #define SPnBase(n) (0xc0120000 + 0x00010000 * (n))
421: #define SP0 0x00
422: #define SP1 0x01
423: #define SPn_MODE(n) (SPnBase(n) + 0x0000)
424: #define SPn_POL(n) (SPnBase(n) + 0x0004)
425: #define SPn_CONTROL(n) (SPnBase(n) + 0x0008)
426: #define SPn_TX_DATA(n) (SPnBase(n) + 0x0010)
427: #define SPn_RX_DATA(n) (SPnBase(n) + 0x0014)
428: #define SPn_STATUS(n) (SPnBase(n) + 0x0018)
429: #define SPn_RAW_STATUS(n) (SPnBase(n) + 0x001c)
430: #define SPn_ENSET(n) (SPnBase(n) + 0x0020)
431: #define SPn_ENCLR(n) (SPnBase(n) + 0x0024)
432: #define SPn_FFCLR(n) (SPnBase(n) + 0x0028)
433: #define SPn_CONTROL2(n) (SPnBase(n) + 0x0034)
434: #define SPn_TIECS(n) (SPnBase(n) + 0x0038)
435:
436: #define CHGREGBase 0xc0140000
437: #define CHG_BOOT_MODE (CHGREGBase + 0x0000)
438: #define CHG_L1_HOLD (CHGREGBase + 0x0004)
439: #define CHG_LSI_REVISION (CHGREGBase + 0x0010)
440: #define CHG_CTRL_SDINT (CHGREGBase + 0x0104)
441: #define CHG_CTRL_AB0_BOOT (CHGREGBase + 0x0108)
442: #define CHG_CTRL_OSC (CHGREGBase + 0x0110)
443: #define CHG_PINSEL_G(n) (CHGREGBase + 0x0200 + 0x0004 * ((n) / 16))
444: #define CHG_PINSEL_SP0 (CHGREGBase + 0x0280)
445: #define CHG_PINSEL_DTV (CHGREGBase + 0x0284)
446: #define CHG_PINSEL_SD0 (CHGREGBase + 0x0288)
447: #define CHG_PINSEL_SD1 (CHGREGBase + 0x028c)
448: #define CHG_PINSEL_IIC2 (CHGREGBase + 0x0290)
449: #define CHG_PINSEL_REFCLKO (CHGREGBase + 0x0294)
450: #define CHG_PULL_G(n) (CHGREGBase + 0x0300 + 0x0004 * ((n) / 8))
451: #define CHG_PULL(n) (CHGREGBase + 0x0380 + 0x0004 * (n))
452: #define CHG_DRIVE(n) (CHGREGBase + 0x0400 + 0x0004 * (n))
453:
454: #define IICBase(x) (0x50030000 + 0x00010000 * (x))
455: #define IIC 0x01
456: #define IIC2 0x00
457: #define IIC_IIC(n) (IICBase(n) + 0x0000)
458: #define IIC_IICC(n) (IICBase(n) + 0x0008)
459: #define IIC_SVA(n) (IICBase(n) + 0x000c)
460: #define IIC_IICCL(n) (IICBase(n) + 0x0010)
461: #define IIC_IICSE(n) (IICBase(n) + 0x001c)
462: #define IIC_IICF(n) (IICBase(n) + 0x0028)
463:
464: #endif