- mtkernel_3
- device/adc/sysdepend/rx231/adc_rx231.c - 6.0KB - 201 lines
144:
145: out_b(MPC_PWPR, 0); // PWPR.B0WI = 0
146: out_b(MPC_PWPR, MPC_PWMR_PFSWE); // PWPR.PFSWE = 1
- More results from adc_rx231.c
- device/adc/sysdepend/rza2m/adc_rza2m.c - 4.7KB - 174 lines
124: stbc = in_b(CPG_STBCR5);
125: out_b(CPG_STBCR5, stbc & 0x7F);
126: stbc = in_b(CPG_STBCR5); // dummy read
- More results from adc_rza2m.c
- device/i2c/sysdepend/rx231/i2c_rx231.c - 11.4KB - 335 lines
56: if(ll_devcb.sdat_num > 0 ) { /* Send */
57: out_b(RIIC_ICDRT, ll_devcb.sadr);
58: ll_devcb.state = I2C_STS_SEND;
- More results from i2c_rx231.c
- device/ser/sysdepend/rx231/ser_rx231.c - 9.0KB - 299 lines
72: if( dev_ser_get_snddat(unit, &data)) {
73: out_b(ba[unit] + SCI_TDR, (UB)data);
74: }
- More results from ser_rx231.c
- device/ser/sysdepend/rza2m/ser_rza2m.c - 10.5KB - 342 lines
77: if( dev_ser_get_snddat(unit, &data)) {
78: out_b(ba[unit] + SCI_FTDR, (UB)data);
79: } else {
- More results from ser_rza2m.c
- kernel/sysdepend/cpu/core/armv7a/sys_timer.h - 2.8KB - 95 lines
35:
36: out_b(OSTM0_TT, 0x01); /* Stop timer */
37: out_b(OSTM0_CTL, 0x01); /* Set Interval timer mode & Interrupt enabled */
- More results from sys_timer.h
- kernel/sysdepend/cpu/rx231/cpu_clock.c - 2.3KB - 68 lines
34:
35: out_b(SYSTEM_MOSCWTCR, 0x05); /* LOCO(4MHz)*16384cyc=4.096ms(Over 3ms) */
36: out_b(SYSTEM_MOSCCR, 0x00); /* Enable Main Clock */
- More results from cpu_clock.c
- kernel/sysdepend/cpu/rza2m/cpu_clock.c - 1.2KB - 53 lines
42: /* Writing to On-Chip Data-Retention RAM is enabled. */
43: out_b(CPG_SYSCR3,0x0F);
44: dummy_8b = in_b(CPG_SYSCR3);
- kernel/sysdepend/iote_rx231/hw_setting.c - 4.0KB - 147 lines
94: /* Setup Pin Function */
95: out_b(MPC_PWPR, 0);
96: out_b(MPC_PWPR, MPC_PWMR_PFSWE); /* Disable Register Protect */
- More results from hw_setting.c
- kernel/sysdepend/iote_rza2m/hw_setting.c - 4.1KB - 139 lines
83: for(p = stbcr_tbl; p->addr != 0; p++) {
84: out_b(p->addr, p->data);
85: dummy_b = in_b(p->addr);
- More results from hw_setting.c