- mtkernel_3
- device/adc/sysdepend/stm32l4/adc_stm32l4.c - 8.0KB - 257 lines
75:
76: out_w(ADC_ISR(unit), 0x000007FF); // Clear all interrupt flag.
77: ClearInt((unit == DEV_ADC_3)?INTNO_INTADC3:INTNO_INTADC1_2);
- More results from adc_stm32l4.c
- device/adc/sysdepend/tx03_m367/adc_m367.c - 4.6KB - 150 lines
63: /* channel fixed single convert */
64: out_w( ba[unit] + ADxMOD3, ADMD_CHFIX_SINGLE); // Ch.Fixed Single mode
65: out_w( ba[unit] + ADxMOD2, ch); // MOD2.ADCH = Channel
- More results from adc_m367.c
- device/i2c/sysdepend/stm32l4/i2c_stm32l4.c - 11.2KB - 330 lines
108: } else if( i2c_st & I2C_ISR_TXIS) { /* TX interrupt */
109: out_w(I2C_TXDR(unit),*p_cb->sbuf++);
110: if(--(p_cb->sdat_num) <= 0) { /* final data ? */
- More results from i2c_stm32l4.c
- device/i2c/sysdepend/tx03_m367/i2c_m367.c - 10.5KB - 305 lines
100: if(p_cb->rdat_num == 1) {
101: out_w(ba[unit] + I2C_SBIxCR1,
102: I2C_SBIxCR1_INIT & ~I2C_SBIxCR1_ACK);
- More results from i2c_m367.c
- device/ser/sysdepend/stm32l4/ser_stm32l4.c - 7.2KB - 215 lines
66:
67: out_w(USART_ICR(unit), USART_ICR_ALL); // Clear Interrupt
68: ClearInt(intno);
- More results from ser_stm32l4.c
- device/ser/sysdepend/tx03_m367/ser_m367.c - 6.2KB - 190 lines
52: /* Clear Interrupt */
53: out_w( ba[unit] + UARTxICR, UARTxINT_ALL);
54:
- More results from ser_m367.c
- kernel/sysdepend/cpu/core/armv7a/interrupt.c - 5.3KB - 143 lines
134:
135: out_w(GICC_PMR, 31<<3); /* Allow all interrupts */
136: out_w(GICC_BPR, 0x00000002UL);
- More results from interrupt.c
- kernel/sysdepend/cpu/core/armv7a/sys_timer.h - 2.8KB - 95 lines
37: out_b(OSTM0_CTL, 0x01); /* Set Interval timer mode & Interrupt enabled */
38: out_w(OSTM0_CMP, (UW)cnt); /* Set compare register */
39: out_b(OSTM0_TS, 0x01); /* Start Timer */
- kernel/sysdepend/cpu/core/armv7m/sys_timer.h - 3.2KB - 108 lines
32: /* Set System timer CLK source to Core, Systick exception enable */
33: out_w(SYST_CSR, 0x00000006);
34:
- More results from sys_timer.h
- kernel/sysdepend/cpu/rx231/cpu_clock.c - 2.3KB - 68 lines
52:
53: out_w(SYSTEM_SCKCR, 0x50860100); /* ICLK=PCLKA=PCLKD:54MHz,PCLKB:27MHz,UCLK:48MHz,FCLK:1.6875MHz */
54: out_h(SYSTEM_SCKCR3, 0x0400); /* Select PLL */